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llvm-project/llvm/test/MC/RISCV/rv32zbr-invalid.s

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[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-10 00:51:10 +08:00
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
# Too many operands
crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
# Too many operands
crc32.h t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
# Too many operands
crc32.w t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
# Too many operands
crc32c.b t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
# Too many operands
crc32c.h t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
# Too many operands
crc32c.w t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
[RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32. Add tests to make sure common instructions are accepted in RV64 and not just RV32. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D95150
2021-01-23 05:30:12 +08:00
crc32.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
crc32c.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set