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llvm-project/llvm/test/MC/RISCV/rv32zbbp-only-valid.s

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[RISCV] Add rv64 run lines to rv32 MC layer tests for B extension Remove common instructions from rv64 tests since they are now covered by the rv64 run lines in the rv32 tests. Add rv32-only* tests for a few cases that aren't common between r32 and rv64. Addresses review feedback from D95150. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D95272
2021-01-27 09:03:21 +08:00
# With Bitmanip base extension:
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" The replacement doesn't work for llc, but it is needed by patchable-function-entry.ll. This reverts commit aa9a30b83a06e3e5e68e32ea645ec2d9edc27efc.
2021-05-29 22:11:37 +08:00
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbb -riscv-no-aliases -show-encoding \
[RISCV] Add rv64 run lines to rv32 MC layer tests for B extension Remove common instructions from rv64 tests since they are now covered by the rv64 run lines in the rv32 tests. Add rv32-only* tests for a few cases that aren't common between r32 and rv64. Addresses review feedback from D95150. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D95272
2021-01-27 09:03:21 +08:00
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip permutation extension:
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbp -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbp < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbp -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: zext.h t0, t1
# CHECK-ASM: encoding: [0xb3,0x42,0x03,0x08]
zext.h t0, t1
# CHECK-ASM-AND-OBJ: rev8 t0, t1
# CHECK-ASM: encoding: [0x93,0x52,0x83,0x69]
rev8 t0, t1