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llvm-project/llvm/test/MC/ARM/invalid-neon-v8.s

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[ARM] Replace fp-only-sp and d16 with fp64 and d32. Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
2019-05-29 00:13:20 +08:00
@ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8d16sp -show-encoding < %s 2>&1 | FileCheck %s
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vmaxnm.f32 s4, d5, q1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vmaxnm.f64.f64 s4, d5, q1
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vmaxnmge.f64.f64 s4, d5, q1
@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
vcvta.s32.f32 s1, s2
[ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options to be more consistent. llvm-svn: 190692
2013-09-13 21:46:57 +08:00
@ CHECK: error: instruction requires: FPARMv8
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtp.u32.f32 s1, d2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [d0, d31]
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtp.f32.u32 d1, q2
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vcvtplo.f32.u32 s1, s2
@ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified
vrinta.f64.f64 s3, d12
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrintn.f32 d3, q12
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
@ CHECK: error: invalid instruction, any one of the following would fix this:
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: note: operand must be a register in range [d0, d31]
@ CHECK: note: operand must be a register in range [q0, q15]
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrintz.f32 d3, q12
[ARM] Use new assembler diags for ARM This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
2017-10-03 18:26:11 +08:00
@ CHECK: error: invalid instruction, any one of the following would fix this:
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: note: operand must be a register in range [d0, d31]
@ CHECK: note: operand must be a register in range [q0, q15]
[ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. llvm-svn: 189341
2013-08-27 19:24:16 +08:00
vrintmge.f32.f32 d3, d4
@ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
aesd.8 q0, s1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
aese.8 s0, q1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
aesimc.8 s0, q1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
aesmc.8 q0, d1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
aesdge.8 q0, q1
@ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
sha1h.32 d0, q1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha1su1.32 q0, s1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha256su0.32 s0, q1
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha1heq.32 q0, q1
@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
sha1c.32 s0, d1, q2
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha1m.32 q0, s1, q2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha1p.32 s0, q1, q2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha1su0.32 d0, q1, q2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha256h.32 q0, s1, q2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha256h2.32 q0, q1, s2
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha256su1.32 s0, d1, q2
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
sha256su1lt.32 q0, d1, q2
@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
vmull.p64 q0, s1, s3
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
2017-12-04 21:42:22 +08:00
@ CHECK: error: invalid instruction
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
vmull.p64 s1, d2, d3
[ARM, Asm] Add diagnostics for floating-point register operands This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
2017-10-10 20:35:09 +08:00
@ CHECK: error: operand must be a register in range [q0, q15]
[ARMv8] Add support for the v8 cryptography extensions. llvm-svn: 190996
2013-09-19 19:59:01 +08:00
vmullge.p64 q0, d16, d17
@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
[ARM] Don't omit non-default predication code This was causing the (invalid) predicated versions of the NEON VRINTX and VRINTZ instructions to be accepted, with the condition code being ignored. Also, there is no NEON VRINTR instruction, so that part of the check was not necessary. Differential revision: https://reviews.llvm.org/D39193 llvm-svn: 318771
2017-11-21 23:34:15 +08:00
// These instructions are predicable in VFP but not in NEON
vrintzeq.f32 d0, d1
vrintxgt.f32 d0, d1
@ CHECK: error: invalid operand for instruction
@ CHECK: error: invalid operand for instruction