MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
//===- MachineInstrTest.cpp -----------------------------------------------===//
|
|
|
|
|
//
|
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
|
//
|
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
|
//
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
|
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
|
|
|
#include "llvm/CodeGen/MachineModuleInfo.h"
|
2017-11-08 09:01:31 +08:00
|
|
|
#include "llvm/CodeGen/TargetFrameLowering.h"
|
|
|
|
|
#include "llvm/CodeGen/TargetInstrInfo.h"
|
2017-11-17 09:07:10 +08:00
|
|
|
#include "llvm/CodeGen/TargetLowering.h"
|
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
2018-01-19 19:44:42 +08:00
|
|
|
#include "llvm/IR/DebugInfoMetadata.h"
|
|
|
|
|
#include "llvm/IR/ModuleSlotTracker.h"
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
|
|
|
#include "llvm/Support/TargetSelect.h"
|
|
|
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
|
#include "llvm/Target/TargetOptions.h"
|
|
|
|
|
#include "gtest/gtest.h"
|
|
|
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
|
// Add a few Bogus backend classes so we can create MachineInstrs without
|
|
|
|
|
// depending on a real target.
|
|
|
|
|
class BogusTargetLowering : public TargetLowering {
|
|
|
|
|
public:
|
|
|
|
|
BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
class BogusFrameLowering : public TargetFrameLowering {
|
|
|
|
|
public:
|
|
|
|
|
BogusFrameLowering()
|
|
|
|
|
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 4) {}
|
|
|
|
|
|
|
|
|
|
void emitPrologue(MachineFunction &MF,
|
|
|
|
|
MachineBasicBlock &MBB) const override {}
|
|
|
|
|
void emitEpilogue(MachineFunction &MF,
|
|
|
|
|
MachineBasicBlock &MBB) const override {}
|
|
|
|
|
bool hasFP(const MachineFunction &MF) const override { return false; }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
class BogusSubtarget : public TargetSubtargetInfo {
|
|
|
|
|
public:
|
|
|
|
|
BogusSubtarget(TargetMachine &TM)
|
|
|
|
|
: TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
|
|
|
|
|
nullptr, nullptr, nullptr, nullptr, nullptr),
|
|
|
|
|
FL(), TL(TM) {}
|
|
|
|
|
~BogusSubtarget() override {}
|
|
|
|
|
|
|
|
|
|
const TargetFrameLowering *getFrameLowering() const override { return &FL; }
|
|
|
|
|
|
|
|
|
|
const TargetLowering *getTargetLowering() const override { return &TL; }
|
|
|
|
|
|
|
|
|
|
const TargetInstrInfo *getInstrInfo() const override { return &TII; }
|
|
|
|
|
|
|
|
|
|
private:
|
|
|
|
|
BogusFrameLowering FL;
|
|
|
|
|
BogusTargetLowering TL;
|
|
|
|
|
TargetInstrInfo TII;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-13 06:57:28 +08:00
|
|
|
class BogusTargetMachine : public LLVMTargetMachine {
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
public:
|
|
|
|
|
BogusTargetMachine()
|
2017-10-13 06:57:28 +08:00
|
|
|
: LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(),
|
|
|
|
|
Reloc::Static, CodeModel::Small, CodeGenOpt::Default),
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
ST(*this) {}
|
|
|
|
|
~BogusTargetMachine() override {}
|
|
|
|
|
|
|
|
|
|
const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
|
|
|
|
|
return &ST;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
private:
|
|
|
|
|
BogusSubtarget ST;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
std::unique_ptr<BogusTargetMachine> createTargetMachine() {
|
|
|
|
|
return llvm::make_unique<BogusTargetMachine>();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
std::unique_ptr<MachineFunction> createMachineFunction() {
|
|
|
|
|
LLVMContext Ctx;
|
|
|
|
|
Module M("Module", Ctx);
|
|
|
|
|
auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
|
|
|
|
|
auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M);
|
|
|
|
|
|
|
|
|
|
auto TM = createTargetMachine();
|
|
|
|
|
unsigned FunctionNum = 42;
|
|
|
|
|
MachineModuleInfo MMI(TM.get());
|
2017-12-16 06:22:46 +08:00
|
|
|
const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F);
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
|
2017-12-16 06:22:46 +08:00
|
|
|
return llvm::make_unique<MachineFunction>(*F, *TM, STI, FunctionNum, MMI);
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
|
|
|
|
|
// for various combinations of IgnoreDefs, and also that it is symmetrical.
|
|
|
|
|
TEST(IsIdenticalToTest, DifferentDefs) {
|
|
|
|
|
auto MF = createMachineFunction();
|
|
|
|
|
|
|
|
|
|
unsigned short NumOps = 2;
|
|
|
|
|
unsigned char NumDefs = 1;
|
|
|
|
|
MCOperandInfo OpInfo[] = {
|
|
|
|
|
{0, 0, MCOI::OPERAND_REGISTER, 0},
|
|
|
|
|
{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
|
|
|
|
|
MCInstrDesc MCID = {
|
|
|
|
|
0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
|
|
|
|
|
0, nullptr, nullptr, OpInfo, 0, nullptr};
|
|
|
|
|
|
|
|
|
|
// Create two MIs with different virtual reg defs and the same uses.
|
|
|
|
|
unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
|
|
|
|
|
unsigned VirtualDef2 = -43;
|
|
|
|
|
unsigned VirtualUse = -44;
|
|
|
|
|
|
|
|
|
|
auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
|
|
|
|
|
MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
|
|
|
|
|
MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
// Check that they are identical when we ignore virtual register defs, but not
|
|
|
|
|
// when we check defs.
|
|
|
|
|
ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
|
|
|
|
|
ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
|
|
|
|
|
|
|
|
|
|
ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
|
|
|
|
|
ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
|
|
|
|
|
|
|
|
|
|
// Create two MIs with different virtual reg defs, and a def or use of a
|
|
|
|
|
// sentinel register.
|
|
|
|
|
unsigned SentinelReg = 0;
|
|
|
|
|
|
|
|
|
|
auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
|
|
|
|
|
MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
|
|
|
|
|
|
|
|
|
|
auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
|
|
|
|
|
MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
// Check that they are never identical.
|
|
|
|
|
ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
|
|
|
|
|
ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
|
|
|
|
|
|
|
|
|
|
ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
|
|
|
|
|
ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
|
|
|
|
|
// MachineInstrExpressionTrait::getHashValue
|
|
|
|
|
void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
|
|
|
|
|
bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
|
|
|
|
|
bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
|
|
|
|
|
|
|
|
|
|
ASSERT_EQ(IsEqual1, IsEqual2);
|
|
|
|
|
|
|
|
|
|
auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
|
|
|
|
|
auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
|
|
|
|
|
|
|
|
|
|
ASSERT_EQ(IsEqual1, Hash1 == Hash2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
|
|
|
|
|
// with MachineInstrExpressionTraits::getHashValue.
|
|
|
|
|
TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
|
|
|
|
|
auto MF = createMachineFunction();
|
|
|
|
|
|
|
|
|
|
unsigned short NumOps = 2;
|
|
|
|
|
unsigned char NumDefs = 1;
|
|
|
|
|
MCOperandInfo OpInfo[] = {
|
|
|
|
|
{0, 0, MCOI::OPERAND_REGISTER, 0},
|
|
|
|
|
{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
|
|
|
|
|
MCInstrDesc MCID = {
|
|
|
|
|
0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
|
|
|
|
|
0, nullptr, nullptr, OpInfo, 0, nullptr};
|
|
|
|
|
|
|
|
|
|
// Define a series of instructions with different kinds of operands and make
|
|
|
|
|
// sure that the hash function is consistent with isEqual for various
|
|
|
|
|
// combinations of them.
|
|
|
|
|
unsigned VirtualDef1 = -42;
|
|
|
|
|
unsigned VirtualDef2 = -43;
|
|
|
|
|
unsigned VirtualReg = -44;
|
|
|
|
|
unsigned SentinelReg = 0;
|
|
|
|
|
unsigned PhysicalReg = 45;
|
|
|
|
|
|
|
|
|
|
auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
VD1VU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
|
|
|
|
|
VD1VU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
VD2VU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
|
|
|
|
|
VD2VU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
VD1SU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
|
|
|
|
|
VD1SU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
VD1SD->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
|
|
|
|
|
VD1SD->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
|
|
|
|
|
|
|
|
|
|
auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
VD2PU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
|
|
|
|
|
VD2PU->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
|
|
|
|
|
|
|
|
|
|
auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
|
|
|
|
|
VD2PD->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
|
|
|
|
|
VD2PD->addOperand(*MF,
|
|
|
|
|
MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
|
|
|
|
|
|
|
|
|
|
checkHashAndIsEqualMatch(VD1VU, VD2VU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1VU, VD1SU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1VU, VD1SD);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1VU, VD2PU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1VU, VD2PD);
|
|
|
|
|
|
|
|
|
|
checkHashAndIsEqualMatch(VD2VU, VD1SU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD2VU, VD1SD);
|
|
|
|
|
checkHashAndIsEqualMatch(VD2VU, VD2PU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD2VU, VD2PD);
|
|
|
|
|
|
|
|
|
|
checkHashAndIsEqualMatch(VD1SU, VD1SD);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1SU, VD2PU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1SU, VD2PD);
|
|
|
|
|
|
|
|
|
|
checkHashAndIsEqualMatch(VD1SD, VD2PU);
|
|
|
|
|
checkHashAndIsEqualMatch(VD1SD, VD2PD);
|
|
|
|
|
|
|
|
|
|
checkHashAndIsEqualMatch(VD2PU, VD2PD);
|
|
|
|
|
}
|
2018-01-19 19:44:42 +08:00
|
|
|
|
|
|
|
|
TEST(MachineInstrPrintingTest, DebugLocPrinting) {
|
|
|
|
|
auto MF = createMachineFunction();
|
|
|
|
|
|
|
|
|
|
MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
|
|
|
|
|
MCInstrDesc MCID = {0, 1, 1, 0, 0, 0,
|
|
|
|
|
0, nullptr, nullptr, &OpInfo, 0, nullptr};
|
|
|
|
|
|
|
|
|
|
LLVMContext Ctx;
|
[CodeGen] Print user-friendly debug locations as MI comments
If available, print the file, line and column of the DebugLoc attached
to the MachineInstr:
MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17
renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17
Differential Revision: https://reviews.llvm.org/D45992
llvm-svn: 330709
2018-04-24 19:00:46 +08:00
|
|
|
DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
|
|
|
|
|
DISubprogram *DIS = DISubprogram::getDistinct(
|
2018-11-20 02:29:28 +08:00
|
|
|
Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
|
|
|
|
|
DISubprogram::SPFlagZero, nullptr);
|
[CodeGen] Print user-friendly debug locations as MI comments
If available, print the file, line and column of the DebugLoc attached
to the MachineInstr:
MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17
renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17
Differential Revision: https://reviews.llvm.org/D45992
llvm-svn: 330709
2018-04-24 19:00:46 +08:00
|
|
|
DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
|
2018-01-19 19:44:42 +08:00
|
|
|
DebugLoc DL(DIL);
|
|
|
|
|
MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
|
|
|
|
|
MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
|
|
|
|
|
|
|
|
|
|
std::string str;
|
|
|
|
|
raw_string_ostream OS(str);
|
|
|
|
|
MI->print(OS);
|
|
|
|
|
ASSERT_TRUE(
|
2018-02-01 06:04:26 +08:00
|
|
|
StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
|
[CodeGen] Print user-friendly debug locations as MI comments
If available, print the file, line and column of the DebugLoc attached
to the MachineInstr:
MOV16mr $rbp, 1, $noreg, -112, $noreg, killed renamable $ax, debug-location !56 :: (store 2 into %ir.._value12); stepping.swift:10:17
renamable $edx = MOVZX32rm16 $rbp, 1, $noreg, -112, $noreg, debug-location !62 :: (dereferenceable load 2 from %ir.._value13); stepping.swift:10:17
Differential Revision: https://reviews.llvm.org/D45992
llvm-svn: 330709
2018-04-24 19:00:46 +08:00
|
|
|
ASSERT_TRUE(
|
|
|
|
|
StringRef(OS.str()).endswith("filename:1:5"));
|
2018-01-19 19:44:42 +08:00
|
|
|
}
|
|
|
|
|
|
MachineInstr: Make isEqual agree with getHashValue in MachineInstrExpressionTrait
MachineInstr::isIdenticalTo has a lot of logic for dealing with register
Defs (i.e. deciding whether to take them into account or ignore them).
This logic gets things wrong in some obscure cases, for instance if an
operand is not a Def for both the current MI and the one we are
comparing to.
I'm not sure if it's possible for this to happen for regular register
operands, but it may happen in the ARM backend for special operands
which use sentinel values for the register (i.e. 0, which is neither a
physical register nor a virtual one).
This causes MachineInstrExpressionTrait::isEqual (which uses
MachineInstr::isIdenticalTo) to return true for the following
instructions, which are the same except for the fact that one sets the
flags and the other one doesn't:
%1114 = ADDrsi %1113, %216, 17, 14, _, def _
%1115 = ADDrsi %1113, %216, 17, 14, _, _
OTOH, MachineInstrExpressionTrait::getHashValue returns different values
for the 2 instructions due to the different isDef on the last operand.
In practice this means that when trying to add those instructions to a
DenseMap, they will be considered different because of their different
hash values, but when growing the map we might get an assertion while
copying from the old buckets to the new buckets because isEqual
misleadingly returns true.
This patch makes sure that isEqual and getHashValue agree, by improving
the checks in MachineInstr::isIdenticalTo when we are ignoring virtual
register definitions (which is what the Trait uses). Firstly, instead of
checking isPhysicalRegister, we use !isVirtualRegister, so that we cover
both physical registers and sentinel values. Secondly, instead of
checking MachineOperand::isReg, we use MachineOperand::isIdenticalTo,
which checks isReg, isSubReg and isDef, which are the same values that
the hash function uses to compute the hash.
Note that the function is symmetric with this change, since if the
current operand is not a Def, we check MachineOperand::isIdenticalTo,
which returns false if the operands have different isDef's.
Differential Revision: https://reviews.llvm.org/D38789
llvm-svn: 315579
2017-10-12 21:59:51 +08:00
|
|
|
} // end namespace
|