maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll

25 lines
1.1 KiB
LLVM
Raw Normal View History

Fix buildbot failures, add mtriple to gpr-vsr-spill.ll llvm-svn: 313890
2017-09-22 01:05:47 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s
[Power9] Spill gprs to vector registers rather than stack This patch updates register allocation to enable spilling gprs to volatile vector registers rather than the stack. It can be enabled for Power9 with option -ppc-enable-gpr-to-vsr-spills. Differential Revision: https://reviews.llvm.org/D34815 llvm-svn: 313886
2017-09-22 00:12:33 +08:00
define signext i32 @foo(i32 signext %a, i32 signext %b) {
entry:
%cmp = icmp slt i32 %a, %b
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b)
%mul = mul nsw i32 %0, %a
%add = add i32 %b, %a
%tmp = add i32 %add, %mul
br label %if.end
if.end: ; preds = %if.then, %entry
%e.0 = phi i32 [ %tmp, %if.then ], [ undef, %entry ]
ret i32 %e.0
; CHECK: @foo
; CHECK: mr [[NEWREG:[0-9]+]], 3
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" Re-enable commit r323991 now that r325931 has been committed to make MachineOperand::isRenamable() check more conservative w.r.t. code changes and opt-in on a per-target basis. llvm-svn: 326208
2018-02-28 00:59:10 +08:00
; CHECK: mr [[REG1:[0-9]+]], 4
[Power9] Spill gprs to vector registers rather than stack This patch updates register allocation to enable spilling gprs to volatile vector registers rather than the stack. It can be enabled for Power9 with option -ppc-enable-gpr-to-vsr-spills. Differential Revision: https://reviews.llvm.org/D34815 llvm-svn: 313886
2017-09-22 00:12:33 +08:00
; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]
}