maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/Mips/mips1/valid.s

241 lines
18 KiB
ArmAsm
Raw Normal View History

[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180
2014-03-31 20:13:12 +08:00
# Instructions that are valid
#
[mips] Properly select abs and sqrt instructions - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
2018-01-23 18:09:39 +08:00
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips1 | FileCheck %s
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
a:
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
.set noat
[mips] Properly select abs and sqrt instructions - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
2018-01-23 18:09:39 +08:00
abs.d $f0,$f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_D32
abs.s $f0,$f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
add $s7,$s2,$a1
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
add.s $f8,$f21,$f24
addi $13,$9,26322
[mips] Update MipsAsmParser so that it's possible to handle immediates that start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 llvm-svn: 211163
2014-06-18 21:55:18 +08:00
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
[mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
2014-09-16 17:26:09 +08:00
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
addu $9,$a0,$a2
[mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
2014-09-16 18:19:03 +08:00
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
and $s7,$v0,$12
[mips] Implement alias for 'and' and 'or' instructions for all ISAs. Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
2014-06-18 21:30:57 +08:00
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
[mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
2014-06-13 21:02:52 +08:00
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
c.ngl.d $f29,$f29
c.ngle.d $f0,$f16
c.sf.d $f30,$f0
c.sf.s $f14,$f22
cfc1 $s1,$21
ctc1 $a2,$26
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
cvt.d.w $f0,$f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_W
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
cvt.s.d $f0,$f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_S_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
cvt.s.w $f22,$f15
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
cvt.w.d $f0,$f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_W_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
cvt.w.s $f20,$f24
div $zero,$25,$11
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
div.s $f4,$f5,$f15
divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} EHB
# CHECK-NOT: # <MCInst #{{[0-9]+}} EHB_MM
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
[mips] Never select JAL for calls to an absolute immediate address. Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
2016-01-11 23:57:46 +08:00
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
lb $24,-14515($10)
lbu $8,30195($v1)
lh $11,-8556($s5)
lhu $s3,-22851($v0)
li $at,-29773
li $zero,-29889
lw $8,5674($a1)
lwc1 $f16,10225($k0)
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
2014-06-16 18:00:45 +08:00
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
lwc3 $10,-32265($k0)
lwl $s4,-4231($15)
lwr $zero,-19147($gp)
mfc1 $a3,$f27
mfhi $s3
mfhi $sp
mflo $s1
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
mov.d $f0,$f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMOV_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
mov.s $f2,$f27
[mips] Remap move as or. Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
2015-08-11 16:56:25 +08:00
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
mtc1 $s8,$f9
mthi $s1
mtlo $sp
mtlo $25
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
mul.d $f0, $f2, $f4 # CHECK: mul.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x02]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FMUL_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
mul.s $f30,$f10,$f2
mult $sp,$s4
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
neg.d $f0,$f2 # CHECK: neg.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x07]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
neg.s $f1,$f15
nop
nor $a3,$zero,$a3
[mips] not instruction alias This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
2016-11-16 19:04:49 +08:00
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
or $12,$s0,$sp
[mips] Implement alias for 'and' and 'or' instructions for all ISAs. Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
2014-06-18 21:30:57 +08:00
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sb $s6,-19857($14)
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sh $14,-6704($15)
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Added missing dsra -> dsrav and sra -> srav aliases. Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
2014-05-09 17:24:49 +08:00
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SSNOP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SSNOP_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sub $s6,$s3,$12
[mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
2014-09-16 17:26:09 +08:00
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
[mips] Define certain instructions in microMIPS32r3 Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
2018-02-08 17:25:17 +08:00
sub.d $f0, $f2, $f4 # CHECK: sub.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x01]
Make test changes added in r324584 more robust by using a regex instead of hard coded MCInst numbers. llvm-svn: 324699
2018-02-09 10:13:15 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSUB_D32
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6
sw $ra,-10160($sp)
swc1 $f6,-8465($24)
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
2014-06-16 18:00:45 +08:00
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
swc3 $10,-32265($k0)
swl $15,13694($s3)
swr $s1,-26590($14)
[mips] Range check uimm20 and fixed a bug this revealed. Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
2016-03-01 00:06:38 +08:00
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
xor $s2,$a0,$s8
[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
2015-03-17 21:17:44 +08:00
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
[mips] added support for trunc macro Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D15745 llvm-svn: 261529
2016-02-23 00:00:23 +08:00
.set at
trunc.w.s $f4,$f6,$4
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: ori $1, $4, 3 # encoding: [0x34,0x81,0x00,0x03]
# CHECK: xori $1, $1, 2 # encoding: [0x38,0x21,0x00,0x02]
# CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: cvt.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x24]
# CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
trunc.w.d $f4,$f6,$4
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: ori $1, $4, 3 # encoding: [0x34,0x81,0x00,0x03]
# CHECK: xori $1, $1, 2 # encoding: [0x38,0x21,0x00,0x02]
# CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: cvt.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x24]
# CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
1:
[mips] Weaken asm predicate for memory offsets The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
2016-05-27 21:56:36 +08:00
# Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
lh $3, %lo(g_8)($2) # CHECK: encoding: [0x84,0x43,A,A]
lhu $3, %lo(g_8)($2) # CHECK: encoding: [0x94,0x43,A,A]
lw $3, %lo(g_8)($2) # CHECK: encoding: [0x8c,0x43,A,A]
sb $3, %lo(g_8)($2) # CHECK: encoding: [0xa0,0x43,A,A]
sh $3, %lo(g_8)($2) # CHECK: encoding: [0xa4,0x43,A,A]
sw $3, %lo(g_8)($2) # CHECK: encoding: [0xac,0x43,A,A]
lwl $3, %lo(g_8)($2) # CHECK: encoding: [0x88,0x43,A,A]
lwr $3, %lo(g_8)($2) # CHECK: encoding: [0x98,0x43,A,A]
swl $3, %lo(g_8)($2) # CHECK: encoding: [0xa8,0x43,A,A]
swr $3, %lo(g_8)($2) # CHECK: encoding: [0xb8,0x43,A,A]
lwc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xc4,0x40,A,A]
swc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xe4,0x40,A,A]
.type g_8,@object
.comm g_8,16,16