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llvm-project/llvm/test/CodeGen/X86/fp128-select.ll

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[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
2019-09-03 04:16:30 +08:00
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=-sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=NOSSE
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=-sse \
; RUN: -enable-legalize-types-checking | FileCheck %s --check-prefix=NOSSE
[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
define void @test_select(fp128* %p, fp128* %q, i1 zeroext %c) {
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
2019-09-03 04:16:30 +08:00
; SSE-LABEL: test_select:
; SSE: # %bb.0:
; SSE-NEXT: testl %edx, %edx
; SSE-NEXT: jne .LBB0_1
; SSE-NEXT: # %bb.2:
; SSE-NEXT: movaps {{.*}}(%rip), %xmm0
; SSE-NEXT: movaps %xmm0, (%rsi)
; SSE-NEXT: retq
; SSE-NEXT: .LBB0_1:
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: movaps %xmm0, (%rsi)
; SSE-NEXT: retq
[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
;
[X86] Enable fp128 as a legal type with SSE1 rather than with MMX. FP128 values are passed in xmm registers so should be asssociated with an SSE feature rather than MMX which uses a different set of registers. llc enables sse1 and sse2 by default with x86_64. But does not enable mmx. Clang enables all 3 features by default. I've tried to add command lines to test with -sse where possible, but any test that returns a value in an xmm register fails with a fatal error with -sse since we have no defined ABI for that scenario. llvm-svn: 370682
2019-09-03 04:16:30 +08:00
; NOSSE-LABEL: test_select:
; NOSSE: # %bb.0:
; NOSSE-NEXT: xorl %eax, %eax
; NOSSE-NEXT: testl %edx, %edx
; NOSSE-NEXT: cmovneq (%rdi), %rax
; NOSSE-NEXT: movabsq $9223231299366420480, %rcx # imm = 0x7FFF800000000000
; NOSSE-NEXT: cmovneq 8(%rdi), %rcx
; NOSSE-NEXT: movq %rcx, 8(%rsi)
; NOSSE-NEXT: movq %rax, (%rsi)
; NOSSE-NEXT: retq
[X86] Accept SELECT op code for x86-64 fp128 type DAGTypeLegalizer::CanSkipSoftenFloatOperand should allow SELECT op code for x86_64 fp128 type for MME targets, so SoftenFloatOperand does not abort on SELECT op code. Differential Revision: http://reviews.llvm.org/D21758 llvm-svn: 275818
2016-07-19 01:20:09 +08:00
%a = load fp128, fp128* %p, align 2
%r = select i1 %c, fp128 %a, fp128 0xL00000000000000007FFF800000000000
store fp128 %r, fp128* %q
ret void
}