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llvm-project/llvm/test/MC/ARM/negative-immediates-fail.s

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[ARM] [Assembler] Support negative immediates for A32, T32 and T16 Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
2017-03-21 22:59:17 +08:00
# RUN: not llvm-mc -triple armv7 %s 2>&1| FileCheck %s
.arm
ADC r0, r1, #0xFFFFFEEE
# CHECK: error: invalid operand for instruction
ADC r0, r1, #0xABFEABFF
# CHECK: error: invalid operand for instruction
ADC r0, r1, #0xFFFFFE02
# CHECK: error: invalid operand for instruction
ADD.W r0, r0, #0xFF01FF01
# CHECK: error: invalid operand for instruction