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llvm-project/llvm/test/CodeGen/Hexagon/macint.ll

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Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that we generate integer multiply accumulate.
[Hexagon] Some cleanup of instruction selection code llvm-svn: 235552
2015-04-23 05:17:00 +08:00
; CHECK: r{{[0-9]+}} {{\+|\-}}= mpyi(r{{[0-9]+}},
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
define i32 @main(i32* %a, i32* %b) nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %a, align 4
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
%div = udiv i32 %0, 10000
%rem = urem i32 %div, 10
store i32 %rem, i32* %b, align 4
ret i32 0
}