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llvm-project/lld/test/ELF/arm-tls-norelax-ld-le.s

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[ELF] Move `// REQUIRES:` line to the top llvm-svn: 335676
2018-06-27 06:20:04 +08:00
// REQUIRES: arm
[ARM] ARM TLS shouldn't use relaxations The ARM TLS relocations are placed on literal data and not the code-sequence, it is therefore not possible to implement the relaxTls* functions. This change updates handleMipsTlsRelocation() to handleNoRelaxTlsRelocation() and incorporates ARM as well as Mips. The ARM support in handleNoRelaxTlsRelocation() currently needs to ouput the module index dynamic relocation in all cases as it is relying on the dynamic linker to set the module index in the got. Should address PR30218 Differential Revision: https://reviews.llvm.org/D24827 llvm-svn: 282250
2016-09-23 21:54:48 +08:00
// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %p/Inputs/arm-tls-get-addr.s -o %t1
// RUN: ld.lld %t1 --shared -o %t1.so
// RUN: llvm-mc %s -o %t.o -filetype=obj -triple=armv7a-linux-gnueabi
[ELF] - Do --hash-style=both by default. Its PR34712, GNU linkers recently changed default values to "both" of "sysv". Patch do the same for all targets except MIPS, where .gnu.hash section is not yet supported. Code suggested by Rui Ueyama. Differential revision: https://reviews.llvm.org/D38407 llvm-svn: 315051
2017-10-06 17:37:44 +08:00
// RUN: ld.lld --hash-style=sysv %t1.so %t.o -o %t
[ELF] Add support for static TLS to ARM The module index dynamic relocation R_ARM_DTPMOD32 is always 1 for an executable. When static linking and when we know that we are not a shared object we can resolve the module index relocation statically. The logic in handleNoRelaxTlsRelocation remains the same for Mips as it has its own custom GOT writing code. For ARM we add the module index relocation to the GOT when it can be resolved statically. In addition the type of the RelExpr for the static resolution of TlsGotRel should be R_TLS and not R_ABS as we need to include the size of the thread control block in the calculation. Addresses the TLS part of PR30218. Differential revision: https://reviews.llvm.org/D27213 llvm-svn: 288153
2016-11-30 00:23:50 +08:00
// RUN: llvm-objdump -s %t | FileCheck %s
[ARM] ARM TLS shouldn't use relaxations The ARM TLS relocations are placed on literal data and not the code-sequence, it is therefore not possible to implement the relaxTls* functions. This change updates handleMipsTlsRelocation() to handleNoRelaxTlsRelocation() and incorporates ARM as well as Mips. The ARM support in handleNoRelaxTlsRelocation() currently needs to ouput the module index dynamic relocation in all cases as it is relying on the dynamic linker to set the module index in the got. Should address PR30218 Differential Revision: https://reviews.llvm.org/D24827 llvm-svn: 282250
2016-09-23 21:54:48 +08:00
.global __tls_get_addr
.text
.p2align 2
.global _start
.syntax unified
.arm
.type _start, %function
_start:
.L0:
bl __tls_get_addr
.word x(tlsldm) + (. - .L0 - 8)
.word x(tlsldo)
.word y(tlsldo)
.section .tbss,"awT",%nobits
.p2align 2
.type y, %object
y:
.space 4
.section .tdata,"awT",%progbits
.p2align 2
.type x, %object
x:
.word 10
[ELF] Add support for static TLS to ARM The module index dynamic relocation R_ARM_DTPMOD32 is always 1 for an executable. When static linking and when we know that we are not a shared object we can resolve the module index relocation statically. The logic in handleNoRelaxTlsRelocation remains the same for Mips as it has its own custom GOT writing code. For ARM we add the module index relocation to the GOT when it can be resolved statically. In addition the type of the RelExpr for the static resolution of TlsGotRel should be R_TLS and not R_ABS as we need to include the size of the thread control block in the calculation. Addresses the TLS part of PR30218. Differential revision: https://reviews.llvm.org/D27213 llvm-svn: 288153
2016-11-30 00:23:50 +08:00
// CHECK: Contents of section .got:
ELF: Place relro sections after non-relro sections in r/w segment. This is in preparation for my next change, which will introduce a relro nobits section. That requires that relro sections appear at the end of the progbits part of the r/w segment so that the relro nobits section can appear contiguously. Because of the amount of churn required in the test suite, I'm making this change separately. llvm-svn: 291523
2017-01-10 09:21:30 +08:00
// CHECK-NEXT: 13064 01000000 00000000