[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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//===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the symbolic operands permitted for various kinds of
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// RISC-V system instruction.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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//===----------------------------------------------------------------------===//
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// CSR (control and status register read/write) instruction options.
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//===----------------------------------------------------------------------===//
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class SysReg<string name, bits<12> op> {
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string Name = name;
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bits<12> Encoding = op;
|
[RISCV] Update debug scratch register names
Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78764
2020-04-24 06:07:03 +08:00
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// A maximum of one alias is supported right now.
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string AltName = name;
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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// FIXME: add these additional fields when needed.
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// Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
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// Privilege Mode: User = 0, System = 1 or Machine = 3.
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// bits<2> ReadWrite = op{11 - 10};
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// bits<2> XMode = op{9 - 8};
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// Check Extra field name and what bits 7-6 correspond to.
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// bits<2> Extra = op{7 - 6};
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// Register number without the privilege bits.
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// bits<6> Number = op{5 - 0};
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code FeaturesRequired = [{ {} }];
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bit isRV32Only = 0;
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}
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def SysRegsList : GenericTable {
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let FilterClass = "SysReg";
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// FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
|
[RISCV] Update debug scratch register names
Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78764
2020-04-24 06:07:03 +08:00
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let Fields = [ "Name", "Encoding", "AltName", "FeaturesRequired", "isRV32Only" ];
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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let PrimaryKey = [ "Encoding" ];
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let PrimaryKeyName = "lookupSysRegByEncoding";
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}
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def lookupSysRegByName : SearchIndex {
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let Table = SysRegsList;
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let Key = [ "Name" ];
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}
|
|
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|
|
|
[RISCV] Update debug scratch register names
Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78764
2020-04-24 06:07:03 +08:00
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def lookupSysRegByAltName : SearchIndex {
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let Table = SysRegsList;
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let Key = [ "AltName" ];
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}
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|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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// The following CSR encodings match those given in Tables 2.2,
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// 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual
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// Volume II: Privileged Architecture.
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//===--------------------------
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// User Trap Setup
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//===--------------------------
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def : SysReg<"ustatus", 0x000>;
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def : SysReg<"uie", 0x004>;
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def : SysReg<"utvec", 0x005>;
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//===--------------------------
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// User Trap Handling
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//===--------------------------
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def : SysReg<"uscratch", 0x040>;
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def : SysReg<"uepc", 0x041>;
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def : SysReg<"ucause", 0x042>;
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def : SysReg<"utval", 0x043>;
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def : SysReg<"uip", 0x044>;
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//===--------------------------
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// User Floating-Point CSRs
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//===--------------------------
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[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: MaskRay, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64139
Patch by James Clarke (jrtc27)
llvm-svn: 365195
2019-07-05 20:16:40 +08:00
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def FFLAGS : SysReg<"fflags", 0x001>;
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def FRM : SysReg<"frm", 0x002>;
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def FCSR : SysReg<"fcsr", 0x003>;
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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//===--------------------------
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// User Counter/Timers
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//===--------------------------
|
[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: MaskRay, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64139
Patch by James Clarke (jrtc27)
llvm-svn: 365195
2019-07-05 20:16:40 +08:00
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def CYCLE : SysReg<"cycle", 0xC00>;
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def TIME : SysReg<"time", 0xC01>;
|
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def INSTRET : SysReg<"instret", 0xC02>;
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
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def : SysReg<"hpmcounter3", 0xC03>;
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def : SysReg<"hpmcounter4", 0xC04>;
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def : SysReg<"hpmcounter5", 0xC05>;
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def : SysReg<"hpmcounter6", 0xC06>;
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def : SysReg<"hpmcounter7", 0xC07>;
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def : SysReg<"hpmcounter8", 0xC08>;
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def : SysReg<"hpmcounter9", 0xC09>;
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def : SysReg<"hpmcounter10", 0xC0A>;
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def : SysReg<"hpmcounter11", 0xC0B>;
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def : SysReg<"hpmcounter12", 0xC0C>;
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def : SysReg<"hpmcounter13", 0xC0D>;
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def : SysReg<"hpmcounter14", 0xC0E>;
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def : SysReg<"hpmcounter15", 0xC0F>;
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def : SysReg<"hpmcounter16", 0xC10>;
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def : SysReg<"hpmcounter17", 0xC11>;
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def : SysReg<"hpmcounter18", 0xC12>;
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def : SysReg<"hpmcounter19", 0xC13>;
|
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def : SysReg<"hpmcounter20", 0xC14>;
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def : SysReg<"hpmcounter21", 0xC15>;
|
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def : SysReg<"hpmcounter22", 0xC16>;
|
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def : SysReg<"hpmcounter23", 0xC17>;
|
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def : SysReg<"hpmcounter24", 0xC18>;
|
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def : SysReg<"hpmcounter25", 0xC19>;
|
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def : SysReg<"hpmcounter26", 0xC1A>;
|
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def : SysReg<"hpmcounter27", 0xC1B>;
|
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def : SysReg<"hpmcounter28", 0xC1C>;
|
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def : SysReg<"hpmcounter29", 0xC1D>;
|
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def : SysReg<"hpmcounter30", 0xC1E>;
|
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def : SysReg<"hpmcounter31", 0xC1F>;
|
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|
|
|
|
|
|
let isRV32Only = 1 in {
|
[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references
Reviewers: asb, lenary
Reviewed By: asb, lenary
Subscribers: MaskRay, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64139
Patch by James Clarke (jrtc27)
llvm-svn: 365195
2019-07-05 20:16:40 +08:00
|
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|
def CYCLEH : SysReg<"cycleh", 0xC80>;
|
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|
def TIMEH : SysReg<"timeh", 0xC81>;
|
|
|
|
|
def INSTRETH : SysReg<"instreth", 0xC82>;
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
|
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def: SysReg<"hpmcounter3h", 0xC83>;
|
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def: SysReg<"hpmcounter4h", 0xC84>;
|
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def: SysReg<"hpmcounter5h", 0xC85>;
|
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def: SysReg<"hpmcounter6h", 0xC86>;
|
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def: SysReg<"hpmcounter7h", 0xC87>;
|
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def: SysReg<"hpmcounter8h", 0xC88>;
|
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def: SysReg<"hpmcounter9h", 0xC89>;
|
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def: SysReg<"hpmcounter10h", 0xC8A>;
|
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def: SysReg<"hpmcounter11h", 0xC8B>;
|
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|
def: SysReg<"hpmcounter12h", 0xC8C>;
|
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def: SysReg<"hpmcounter13h", 0xC8D>;
|
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|
def: SysReg<"hpmcounter14h", 0xC8E>;
|
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def: SysReg<"hpmcounter15h", 0xC8F>;
|
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|
|
def: SysReg<"hpmcounter16h", 0xC90>;
|
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|
def: SysReg<"hpmcounter17h", 0xC91>;
|
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|
|
def: SysReg<"hpmcounter18h", 0xC92>;
|
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|
|
|
def: SysReg<"hpmcounter19h", 0xC93>;
|
|
|
|
|
def: SysReg<"hpmcounter20h", 0xC94>;
|
|
|
|
|
def: SysReg<"hpmcounter21h", 0xC95>;
|
|
|
|
|
def: SysReg<"hpmcounter22h", 0xC96>;
|
|
|
|
|
def: SysReg<"hpmcounter23h", 0xC97>;
|
|
|
|
|
def: SysReg<"hpmcounter24h", 0xC98>;
|
|
|
|
|
def: SysReg<"hpmcounter25h", 0xC99>;
|
|
|
|
|
def: SysReg<"hpmcounter26h", 0xC9A>;
|
|
|
|
|
def: SysReg<"hpmcounter27h", 0xC9B>;
|
|
|
|
|
def: SysReg<"hpmcounter28h", 0xC9C>;
|
|
|
|
|
def: SysReg<"hpmcounter29h", 0xC9D>;
|
|
|
|
|
def: SysReg<"hpmcounter30h", 0xC9E>;
|
|
|
|
|
def: SysReg<"hpmcounter31h", 0xC9F>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//===--------------------------
|
|
|
|
|
// Supervisor Trap Setup
|
|
|
|
|
//===--------------------------
|
|
|
|
|
def : SysReg<"sstatus", 0x100>;
|
|
|
|
|
def : SysReg<"sedeleg", 0x102>;
|
|
|
|
|
def : SysReg<"sideleg", 0x103>;
|
|
|
|
|
def : SysReg<"sie", 0x104>;
|
|
|
|
|
def : SysReg<"stvec", 0x105>;
|
|
|
|
|
def : SysReg<"scounteren", 0x106>;
|
|
|
|
|
|
|
|
|
|
//===--------------------------
|
|
|
|
|
// Supervisor Trap Handling
|
|
|
|
|
//===--------------------------
|
|
|
|
|
def : SysReg<"sscratch", 0x140>;
|
|
|
|
|
def : SysReg<"sepc", 0x141>;
|
|
|
|
|
def : SysReg<"scause", 0x142>;
|
|
|
|
|
def : SysReg<"stval", 0x143>;
|
|
|
|
|
def : SysReg<"sip", 0x144>;
|
|
|
|
|
|
|
|
|
|
//===-------------------------------------
|
|
|
|
|
// Supervisor Protection and Translation
|
|
|
|
|
//===-------------------------------------
|
|
|
|
|
def : SysReg<"satp", 0x180>;
|
|
|
|
|
|
|
|
|
|
//===-----------------------------
|
|
|
|
|
// Machine Information Registers
|
|
|
|
|
//===-----------------------------
|
|
|
|
|
|
|
|
|
|
def : SysReg<"mvendorid", 0xF11>;
|
|
|
|
|
def : SysReg<"marchid", 0xF12>;
|
|
|
|
|
def : SysReg<"mimpid", 0xF13>;
|
|
|
|
|
def : SysReg<"mhartid", 0xF14>;
|
|
|
|
|
|
|
|
|
|
//===-----------------------------
|
|
|
|
|
// Machine Trap Setup
|
|
|
|
|
//===-----------------------------
|
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|
|
def : SysReg<"mstatus", 0x300>;
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|
def : SysReg<"misa", 0x301>;
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|
def : SysReg<"medeleg", 0x302>;
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|
def : SysReg<"mideleg", 0x303>;
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|
def : SysReg<"mie", 0x304>;
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def : SysReg<"mtvec", 0x305>;
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|
def : SysReg<"mcounteren", 0x306>;
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|
//===-----------------------------
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|
|
// Machine Trap Handling
|
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|
//===-----------------------------
|
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|
def : SysReg<"mscratch", 0x340>;
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|
def : SysReg<"mepc", 0x341>;
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|
def : SysReg<"mcause", 0x342>;
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|
def : SysReg<"mtval", 0x343>;
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|
def : SysReg<"mip", 0x344>;
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|
//===----------------------------------
|
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|
|
// Machine Protection and Translation
|
|
|
|
|
//===----------------------------------
|
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|
|
def : SysReg<"pmpcfg0", 0x3A0>;
|
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|
def : SysReg<"pmpcfg2", 0x3A2>;
|
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|
|
|
let isRV32Only = 1 in {
|
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|
|
|
def : SysReg<"pmpcfg1", 0x3A1>;
|
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|
def : SysReg<"pmpcfg3", 0x3A3>;
|
|
|
|
|
}
|
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|
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|
|
def : SysReg<"pmpaddr0", 0x3B0>;
|
|
|
|
|
def : SysReg<"pmpaddr1", 0x3B1>;
|
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|
|
|
def : SysReg<"pmpaddr2", 0x3B2>;
|
|
|
|
|
def : SysReg<"pmpaddr3", 0x3B3>;
|
|
|
|
|
def : SysReg<"pmpaddr4", 0x3B4>;
|
|
|
|
|
def : SysReg<"pmpaddr5", 0x3B5>;
|
|
|
|
|
def : SysReg<"pmpaddr6", 0x3B6>;
|
|
|
|
|
def : SysReg<"pmpaddr7", 0x3B7>;
|
|
|
|
|
def : SysReg<"pmpaddr8", 0x3B8>;
|
|
|
|
|
def : SysReg<"pmpaddr9", 0x3B9>;
|
|
|
|
|
def : SysReg<"pmpaddr10", 0x3BA>;
|
|
|
|
|
def : SysReg<"pmpaddr11", 0x3BB>;
|
|
|
|
|
def : SysReg<"pmpaddr12", 0x3BC>;
|
|
|
|
|
def : SysReg<"pmpaddr13", 0x3BD>;
|
|
|
|
|
def : SysReg<"pmpaddr14", 0x3BE>;
|
|
|
|
|
def : SysReg<"pmpaddr15", 0x3BF>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//===--------------------------
|
|
|
|
|
// Machine Counter and Timers
|
|
|
|
|
//===--------------------------
|
|
|
|
|
def : SysReg<"mcycle", 0xB00>;
|
|
|
|
|
def : SysReg<"minstret", 0xB02>;
|
|
|
|
|
|
|
|
|
|
def : SysReg<"mhpmcounter3", 0xB03>;
|
|
|
|
|
def : SysReg<"mhpmcounter4", 0xB04>;
|
|
|
|
|
def : SysReg<"mhpmcounter5", 0xB05>;
|
|
|
|
|
def : SysReg<"mhpmcounter6", 0xB06>;
|
|
|
|
|
def : SysReg<"mhpmcounter7", 0xB07>;
|
|
|
|
|
def : SysReg<"mhpmcounter8", 0xB08>;
|
|
|
|
|
def : SysReg<"mhpmcounter9", 0xB09>;
|
|
|
|
|
def : SysReg<"mhpmcounter10", 0xB0A>;
|
|
|
|
|
def : SysReg<"mhpmcounter11", 0xB0B>;
|
|
|
|
|
def : SysReg<"mhpmcounter12", 0xB0C>;
|
|
|
|
|
def : SysReg<"mhpmcounter13", 0xB0D>;
|
|
|
|
|
def : SysReg<"mhpmcounter14", 0xB0E>;
|
|
|
|
|
def : SysReg<"mhpmcounter15", 0xB0F>;
|
|
|
|
|
def : SysReg<"mhpmcounter16", 0xB10>;
|
|
|
|
|
def : SysReg<"mhpmcounter17", 0xB11>;
|
|
|
|
|
def : SysReg<"mhpmcounter18", 0xB12>;
|
|
|
|
|
def : SysReg<"mhpmcounter19", 0xB13>;
|
|
|
|
|
def : SysReg<"mhpmcounter20", 0xB14>;
|
|
|
|
|
def : SysReg<"mhpmcounter21", 0xB15>;
|
|
|
|
|
def : SysReg<"mhpmcounter22", 0xB16>;
|
|
|
|
|
def : SysReg<"mhpmcounter23", 0xB17>;
|
|
|
|
|
def : SysReg<"mhpmcounter24", 0xB18>;
|
|
|
|
|
def : SysReg<"mhpmcounter25", 0xB19>;
|
|
|
|
|
def : SysReg<"mhpmcounter26", 0xB1A>;
|
|
|
|
|
def : SysReg<"mhpmcounter27", 0xB1B>;
|
|
|
|
|
def : SysReg<"mhpmcounter28", 0xB1C>;
|
|
|
|
|
def : SysReg<"mhpmcounter29", 0xB1D>;
|
|
|
|
|
def : SysReg<"mhpmcounter30", 0xB1E>;
|
|
|
|
|
def : SysReg<"mhpmcounter31", 0xB1F>;
|
|
|
|
|
|
|
|
|
|
let isRV32Only = 1 in {
|
|
|
|
|
def: SysReg<"mcycleh", 0xB80>;
|
|
|
|
|
def: SysReg<"minstreth", 0xB82>;
|
|
|
|
|
|
|
|
|
|
def: SysReg<"mhpmcounter3h", 0xB83>;
|
|
|
|
|
def: SysReg<"mhpmcounter4h", 0xB84>;
|
|
|
|
|
def: SysReg<"mhpmcounter5h", 0xB85>;
|
|
|
|
|
def: SysReg<"mhpmcounter6h", 0xB86>;
|
|
|
|
|
def: SysReg<"mhpmcounter7h", 0xB87>;
|
|
|
|
|
def: SysReg<"mhpmcounter8h", 0xB88>;
|
|
|
|
|
def: SysReg<"mhpmcounter9h", 0xB89>;
|
|
|
|
|
def: SysReg<"mhpmcounter10h", 0xB8A>;
|
|
|
|
|
def: SysReg<"mhpmcounter11h", 0xB8B>;
|
|
|
|
|
def: SysReg<"mhpmcounter12h", 0xB8C>;
|
|
|
|
|
def: SysReg<"mhpmcounter13h", 0xB8D>;
|
|
|
|
|
def: SysReg<"mhpmcounter14h", 0xB8E>;
|
|
|
|
|
def: SysReg<"mhpmcounter15h", 0xB8F>;
|
|
|
|
|
def: SysReg<"mhpmcounter16h", 0xB90>;
|
|
|
|
|
def: SysReg<"mhpmcounter17h", 0xB91>;
|
|
|
|
|
def: SysReg<"mhpmcounter18h", 0xB92>;
|
|
|
|
|
def: SysReg<"mhpmcounter19h", 0xB93>;
|
|
|
|
|
def: SysReg<"mhpmcounter20h", 0xB94>;
|
|
|
|
|
def: SysReg<"mhpmcounter21h", 0xB95>;
|
|
|
|
|
def: SysReg<"mhpmcounter22h", 0xB96>;
|
|
|
|
|
def: SysReg<"mhpmcounter23h", 0xB97>;
|
|
|
|
|
def: SysReg<"mhpmcounter24h", 0xB98>;
|
|
|
|
|
def: SysReg<"mhpmcounter25h", 0xB99>;
|
|
|
|
|
def: SysReg<"mhpmcounter26h", 0xB9A>;
|
|
|
|
|
def: SysReg<"mhpmcounter27h", 0xB9B>;
|
|
|
|
|
def: SysReg<"mhpmcounter28h", 0xB9C>;
|
|
|
|
|
def: SysReg<"mhpmcounter29h", 0xB9D>;
|
|
|
|
|
def: SysReg<"mhpmcounter30h", 0xB9E>;
|
|
|
|
|
def: SysReg<"mhpmcounter31h", 0xB9F>;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//===--------------------------
|
|
|
|
|
// Machine Counter Setup
|
|
|
|
|
//===--------------------------
|
[RISCV] Add mcountinhibit CSR
Summary:
The mcountinhibit CSR is defined in the ratified 1.11 version of the privileged
spec.
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82913
2020-07-01 05:32:37 +08:00
|
|
|
def : SysReg<"mcountinhibit", 0x320>;
|
[RISCV] Support named operands for CSR instructions.
Reviewers: asb, mgrang
Reviewed By: asb
Subscribers: jocewei, mgorny, jfb, PkmX, MartinMosbeck, brucehoult, the_o, rkruppe, rogfer01, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones
Differential Revision: https://reviews.llvm.org/D46759
llvm-svn: 343822
2018-10-05 05:50:54 +08:00
|
|
|
def : SysReg<"mhpmevent3", 0x323>;
|
|
|
|
|
def : SysReg<"mhpmevent4", 0x324>;
|
|
|
|
|
def : SysReg<"mhpmevent5", 0x325>;
|
|
|
|
|
def : SysReg<"mhpmevent6", 0x326>;
|
|
|
|
|
def : SysReg<"mhpmevent7", 0x327>;
|
|
|
|
|
def : SysReg<"mhpmevent8", 0x328>;
|
|
|
|
|
def : SysReg<"mhpmevent9", 0x329>;
|
|
|
|
|
def : SysReg<"mhpmevent10", 0x32A>;
|
|
|
|
|
def : SysReg<"mhpmevent11", 0x32B>;
|
|
|
|
|
def : SysReg<"mhpmevent12", 0x32C>;
|
|
|
|
|
def : SysReg<"mhpmevent13", 0x32D>;
|
|
|
|
|
def : SysReg<"mhpmevent14", 0x32E>;
|
|
|
|
|
def : SysReg<"mhpmevent15", 0x32F>;
|
|
|
|
|
def : SysReg<"mhpmevent16", 0x330>;
|
|
|
|
|
def : SysReg<"mhpmevent17", 0x331>;
|
|
|
|
|
def : SysReg<"mhpmevent18", 0x332>;
|
|
|
|
|
def : SysReg<"mhpmevent19", 0x333>;
|
|
|
|
|
def : SysReg<"mhpmevent20", 0x334>;
|
|
|
|
|
def : SysReg<"mhpmevent21", 0x335>;
|
|
|
|
|
def : SysReg<"mhpmevent22", 0x336>;
|
|
|
|
|
def : SysReg<"mhpmevent23", 0x337>;
|
|
|
|
|
def : SysReg<"mhpmevent24", 0x338>;
|
|
|
|
|
def : SysReg<"mhpmevent25", 0x339>;
|
|
|
|
|
def : SysReg<"mhpmevent26", 0x33A>;
|
|
|
|
|
def : SysReg<"mhpmevent27", 0x33B>;
|
|
|
|
|
def : SysReg<"mhpmevent28", 0x33C>;
|
|
|
|
|
def : SysReg<"mhpmevent29", 0x33D>;
|
|
|
|
|
def : SysReg<"mhpmevent30", 0x33E>;
|
|
|
|
|
def : SysReg<"mhpmevent31", 0x33F>;
|
|
|
|
|
|
|
|
|
|
//===-----------------------------------------------
|
|
|
|
|
// Debug/ Trace Registers (shared with Debug Mode)
|
|
|
|
|
//===-----------------------------------------------
|
|
|
|
|
def : SysReg<"tselect", 0x7A0>;
|
|
|
|
|
def : SysReg<"tdata1", 0x7A1>;
|
|
|
|
|
def : SysReg<"tdata2", 0x7A2>;
|
|
|
|
|
def : SysReg<"tdata3", 0x7A3>;
|
|
|
|
|
|
|
|
|
|
//===-----------------------------------------------
|
|
|
|
|
// Debug Mode Registers
|
|
|
|
|
//===-----------------------------------------------
|
|
|
|
|
def : SysReg<"dcsr", 0x7B0>;
|
|
|
|
|
def : SysReg<"dpc", 0x7B1>;
|
2019-10-24 12:29:28 +08:00
|
|
|
|
[RISCV] Update debug scratch register names
Summary:
The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.
Reviewers: apazos, asb, lenary, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78764
2020-04-24 06:07:03 +08:00
|
|
|
// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
|
|
|
|
|
// drafts of the RISC-V debug spec
|
|
|
|
|
let AltName = "dscratch" in
|
|
|
|
|
def : SysReg<"dscratch0", 0x7B2>;
|
|
|
|
|
def : SysReg<"dscratch1", 0x7B3>;
|
2019-10-24 12:29:28 +08:00
|
|
|
|
|
|
|
|
//===-----------------------------------------------
|
|
|
|
|
// User Vector CSRs
|
|
|
|
|
//===-----------------------------------------------
|
|
|
|
|
def : SysReg<"vstart", 0x008>;
|
|
|
|
|
def : SysReg<"vxsat", 0x009>;
|
|
|
|
|
def : SysReg<"vxrm", 0x00A>;
|
|
|
|
|
def : SysReg<"vl", 0xC20>;
|
|
|
|
|
def : SysReg<"vtype", 0xC21>;
|
|
|
|
|
def : SysReg<"vlenb", 0xC22>;
|
