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llvm-project/llvm/test/MC/Disassembler/X86/x86-64.txt

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Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
# Coverage
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_usps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x04 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_uspd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x05 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_usss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x06 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_ussd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x07 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x04 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x05 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x06 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x07 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x04 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x05 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x06 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x07 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x66 0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf3 0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf2 0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x0f 0xc2 0xc7 0x07
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x66 0x0f 0xc2 0xc7 0x07
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf3 0x0f 0xc2 0xc7 0x07
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf2 0x0f 0xc2 0xc7 0x07
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
2012-05-30 03:05:25 +08:00
# CHECK: extrq $2, $3, %xmm0
0x66 0x0f 0x78 0xc0 0x03 0x02
# CHECK: extrq %xmm1, %xmm0
0x66 0x0f 0x79 0xc1
# CHECK: insertq $6, $5, %xmm1, %xmm0
0xf2 0x0f 0x78 0xc1 0x05 0x06
# CHECK: insertq %xmm1, %xmm0
0xf2 0x0f 0x79 0xc1
# CHECK: movntsd %xmm0, (%rdi)
0xf2 0x0f 0x2b 0x07
# CHECK: movntss %xmm0, (%rdi)
0xf3 0x0f 0x2b 0x07
added basic support for Intel ADX instructions -feature flag, instructions definitions, test cases llvm-svn: 175196
2013-02-15 03:08:21 +08:00
# CHECK: adcxl %eax, %eax
0x66 0x0f 0x38 0xf6 0xc0
# CHECK: adcxl (%rax), %eax
0x66 0x0f 0x38 0xf6 0x00
# CHECK: adcxq %rax, %rax
0x66 0x48 0x0f 0x38 0xf6 0xc0
# CHECK: adcxq (%rax), %rax
0x66 0x48 0x0f 0x38 0xf6 0x00
# CHECK: adoxl %eax, %eax
0xf3 0x0f 0x38 0xf6 0xc0
# CHECK: adoxl (%rax), %eax
0xf3 0x0f 0x38 0xf6 0x00
# CHECK: adoxq %rax, %rax
0xf3 0x48 0x0f 0x38 0xf6 0xc0
# CHECK: adoxq (%rax), %rax
0xf3 0x48 0x0f 0x38 0xf6 0x00
Fixes disassembler crashes on 2013 Haswell RTM instructions. rdar://13318048 llvm-svn: 176828
2013-03-12 05:17:13 +08:00
# CHECK: xbegin 53
0xc7 0xf8 0x35 0x00 0x00 0x00
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
2015-01-06 16:59:30 +08:00
# CHECK: xbegin 53
0x66 0xc7 0xf8 0x35 0x00
Fixes disassembler crashes on 2013 Haswell RTM instructions. rdar://13318048 llvm-svn: 176828
2013-03-12 05:17:13 +08:00
# CHECK: xend
0x0f 0x01 0xd5
# CHECK: xabort $13
0xc6 0xf8 0x0d
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 19:03:57 +08:00
# CHECK: xsave64 (%rax)
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
0x48 0x0f 0xae 0x20
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 19:03:57 +08:00
# CHECK: xrstor64 (%rax)
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
0x48 0x0f 0xae 0x28
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 19:03:57 +08:00
# CHECK: xsaveopt64 (%rax)
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
0x48 0x0f 0xae 0x30
Add CLAC/STAC instruction encoding/decoding support As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
2013-04-11 12:52:28 +08:00
# CHECK: clac
0x0f 0x01 0xca
# CHECK: stac
0x0f 0x01 0xcb
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
# CHECK: movabsb -6066930261531658096, %al
0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb -6066930261531658096, %al
0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsw -6066930261531658096, %ax
0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsl -6066930261531658096, %eax
0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsq -6066930261531658096, %rax
0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb %al, -6066930261531658096
0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb %al, -6066930261531658096
0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsw %ax, -6066930261531658096
0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsl %eax, -6066930261531658096
0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsq %rax, -6066930261531658096
0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
Partial support for Intel SHA Extensions (sha1rnds4) Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
2013-09-12 23:51:31 +08:00
# CHECK: sha1rnds4 $1, %xmm1, %xmm2
0x0f 0x3a 0xcc 0xd1 0x01
# CHECK: sha1rnds4 $1, (%rax), %xmm2
Add the remaining Intel SHA instructions Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
2013-09-14 23:03:21 +08:00
0x0f 0x3a 0xcc 0x10 0x01
# CHECK: sha1nexte %xmm1, %xmm2
0x0f 0x38 0xc8 0xd1
# CHECK: sha1nexte (%rax), %xmm2
0x0f 0x38 0xc8 0x10
# CHECK: sha1msg1 %xmm1, %xmm2
0x0f 0x38 0xc9 0xd1
# CHECK: sha1msg1 (%rax), %xmm2
0x0f 0x38 0xc9 0x10
# CHECK: sha1msg2 %xmm1, %xmm2
0x0f 0x38 0xca 0xd1
# CHECK: sha1msg2 (%rax), %xmm2
0x0f 0x38 0xca 0x10
[X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument. llvm-svn: 294132
2017-02-06 02:33:31 +08:00
# CHECK: sha256rnds2 %xmm0, (%rax), %xmm2
Add the remaining Intel SHA instructions Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
2013-09-14 23:03:21 +08:00
0x0f 0x38 0xcb 0x10
[X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument. llvm-svn: 294132
2017-02-06 02:33:31 +08:00
# CHECK: sha256rnds2 %xmm0, %xmm1, %xmm2
Add the remaining Intel SHA instructions Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
2013-09-14 23:03:21 +08:00
0x0f 0x38 0xcb 0xd1
# CHECK: sha256msg1 %xmm1, %xmm2
0x0f 0x38 0xcc 0xd1
# CHECK: sha256msg1 (%rax), %xmm2
0x0f 0x38 0xcc 0x10
# CHECK: sha256msg2 %xmm1, %xmm2
0x0f 0x38 0xcd 0xd1
# CHECK: sha256msg2 (%rax), %xmm2
Add disassembler support for long encodings for INC/DEC in 32-bit mode. llvm-svn: 192086
2013-10-07 12:28:06 +08:00
0x0f 0x38 0xcd 0x10
# CHECK: incl %ecx
0xff 0xc1
# CHECK: decl %ecx
0xff 0xc9
# CHECK: incw %cx
0x66 0xff 0xc1
# CHECK: decw %cx
0x66 0xff 0xc9
# CHECK: incb %cl
0xfe 0xc1
# CHECK: decb %cl
0xfe 0xc9
# CHECK: incq %rcx
0x48 0xff 0xc1
# CHECK: decq %rcx
0x48 0xff 0xc9
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
2013-10-07 15:19:47 +08:00
# CHECK: movq %xmm0, %xmm0
0xf3 0x0f 0x7e 0xc0
# CHECK: vmovq %xmm0, %xmm0
0xc5 0xfa 0x7e 0xc0
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
2013-10-08 13:53:50 +08:00
# CHECK: vmovq %xmm0, %rax
0xc4 0xe1 0xf9 0x7e 0xc0
[X86] Add some missing redundant MMX and SSE encodings for disassembler. llvm-svn: 230165
2015-02-22 15:50:41 +08:00
# CHECK: movd (%rax), %mm0
0x48 0x0f 0x6e 0x00
# CHECK: movd %rax, %mm0
0x48 0x0f 0x6e 0xc0
# CHECK: movd %mm0, (%rax)
0x48 0x0f 0x7e 0x00
# CHECK: movd %mm0, %rax
0x48 0x0f 0x7e 0xc0
[X86][SSE2] Fix asm string for movq (Move Quadword) instruction. Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
2017-04-26 15:08:44 +08:00
# CHECK: movq (%rax), %xmm0
[X86] Add some missing redundant MMX and SSE encodings for disassembler. llvm-svn: 230165
2015-02-22 15:50:41 +08:00
0x66 0x48 0x0f 0x6e 0x00
[X86][SSE2] Fix asm string for movq (Move Quadword) instruction. Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
2017-04-26 15:08:44 +08:00
# CHECK: movq %rax, %xmm0
[X86] Add some missing redundant MMX and SSE encodings for disassembler. llvm-svn: 230165
2015-02-22 15:50:41 +08:00
0x66 0x48 0x0f 0x6e 0xc0
[X86][SSE2] Fix asm string for movq (Move Quadword) instruction. Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
2017-04-26 15:08:44 +08:00
# CHECK: movq %xmm0, (%rax)
[X86] Add some missing redundant MMX and SSE encodings for disassembler. llvm-svn: 230165
2015-02-22 15:50:41 +08:00
0x66 0x48 0x0f 0x7e 0x00
[X86][SSE2] Fix asm string for movq (Move Quadword) instruction. Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
2017-04-26 15:08:44 +08:00
# CHECK: movq %xmm0, %rax
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
2013-10-08 13:53:50 +08:00
0x66 0x48 0x0f 0x7e 0xc0
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. llvm-svn: 192566
2013-10-14 09:42:32 +08:00
# CHECK: pextrw $3, %xmm3, %ecx
0x66 0x0f 0x3a 0x15 0xd9 0x03
# CHECK: pextrw $3, %xmm3, (%rax)
0x66 0x0f 0x3a 0x15 0x18 0x03
Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. llvm-svn: 201507
2014-02-17 18:03:43 +08:00
# CHECK: $0, 305419896(,%r8)
0x43 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%r13,%r8)
0x43 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(,%r8)
0x42 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp,%r8)
0x42 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(,%r12)
0x42 0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp,%r12)
0x42 0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896
0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp)
0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. llvm-svn: 225099
2015-01-03 08:00:20 +08:00
# CHECK: movabsq 6510615555426900570, %rax
0x48 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
# CHECK: movq 1515870810, %rax
0x67, 0x48 0xa1 0x5a 0x5a 0x5a 0x5a
# CHECK: movabsq %rax, 6510615555426900570
0x48 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
# CHECK: movq %rax, 1515870810
0x67, 0x48 0xa3 0x5a 0x5a 0x5a 0x5a
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler. Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
2015-05-14 06:44:52 +08:00
[llvm-mc] Ignore opcode size prefix in 64-bit CALL disassembly This is a fix for disassembling unusual instruction sequences in 64-bit mode w.r.t the CALL rel16 instruction. It might be desirable to move the check somewhere else, but it essentially mimics the special case handling with JCXZ in 16-bit mode. The current behavior accepts the opcode size prefix and causes the call's immediate to stop disassembling after 2 bytes. When debugging sequences of instructions with this pattern, the disassembler output becomes extremely unreliable and essentially useless (if you jump midway into what lldb thinks is a unified instruction, you'll lose %rip). So we ignore the prefix and consume all 4 bytes when disassembling a 64-bit mode binary. Note: in Vol. 2A 3-99 the Intel spec states that CALL rel16 is N.S. N.S. is defined as: Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. (Vol. 2A 3-7) Since 0x66 is an operand override prefix we should be OK (although we may want to warn about 0x67 prefixes to 0xe8). On the CPUs I tested with, they all ignore the 0x66 prefix in 64-bit mode. Patch by Matthew Barney! Differential Revision: http://reviews.llvm.org/D9573 llvm-svn: 246038
2015-08-27 00:20:29 +08:00
# CHECK: callq -32769
0x66 0xe8 0xff 0x7f 0xff 0xff
# CHECK: callq -32769
0x66 0x66 0x48 0xe8 0xff 0x7f 0xff 0xff
# CHECK: jmp -32769
0xe9 0xff 0x7f 0xff 0xff
# CHECK: jmp -32769
0x66 0xe9 0xff 0x7f 0xff 0xff
# CHECK: jmp -32769
0x66 0x66 0x48 0xe9 0xff 0x7f 0xff 0xff
# CHECK: jb -32769
0x0f 0x82 0xff 0x7f 0xff 0xff
# CHECK: jb -32769
0x66 0x0f 0x82 0xff 0x7f 0xff 0xff
# CHECK: jae -32769
0x0f 0x83 0xff 0x7f 0xff 0xff
# CHECK: jae -32769
0x66 0x0f 0x83 0xff 0x7f 0xff 0xff
# CHECK: je -32769
0x0f 0x84 0xff 0x7f 0xff 0xff
# CHECK: je -32769
0x66 0x0f 0x84 0xff 0x7f 0xff 0xff
# CHECK: jne -32769
0x0f 0x85 0xff 0x7f 0xff 0xff
# CHECK: jne -32769
0x66 0x0f 0x85 0xff 0x7f 0xff 0xff
# CHECK: jbe -32769
0x0f 0x86 0xff 0x7f 0xff 0xff
# CHECK: jbe -32769
0x66 0x0f 0x86 0xff 0x7f 0xff 0xff
# CHECK: ja -32769
0x0f 0x87 0xff 0x7f 0xff 0xff
# CHECK: ja -32769
0x66 0x0f 0x87 0xff 0x7f 0xff 0xff
# CHECK: js -32769
0x0f 0x88 0xff 0x7f 0xff 0xff
# CHECK: js -32769
0x66 0x0f 0x88 0xff 0x7f 0xff 0xff
# CHECK: jns -32769
0x0f 0x89 0xff 0x7f 0xff 0xff
# CHECK: jns -32769
0x66 0x0f 0x89 0xff 0x7f 0xff 0xff
# CHECK: jp -32769
0x0f 0x8a 0xff 0x7f 0xff 0xff
# CHECK: jp -32769
0x66 0x0f 0x8a 0xff 0x7f 0xff 0xff
# CHECK: jnp -32769
0x0f 0x8b 0xff 0x7f 0xff 0xff
# CHECK: jnp -32769
0x66 0x0f 0x8b 0xff 0x7f 0xff 0xff
# CHECK: jl -32769
0x0f 0x8c 0xff 0x7f 0xff 0xff
# CHECK: jl -32769
0x66 0x0f 0x8c 0xff 0x7f 0xff 0xff
# CHECK: jge -32769
0x0f 0x8d 0xff 0x7f 0xff 0xff
# CHECK: jge -32769
0x66 0x0f 0x8d 0xff 0x7f 0xff 0xff
# CHECK: jle -32769
0x0f 0x8e 0xff 0x7f 0xff 0xff
# CHECK: jle -32769
0x66 0x0f 0x8e 0xff 0x7f 0xff 0xff
# CHECK: jg -32769
0x0f 0x8f 0xff 0x7f 0xff 0xff
# CHECK: jg -32769
0x66 0x0f 0x8f 0xff 0x7f 0xff 0xff
# CHECK: lcallw *-32769(%rip)
0x66 0xff 0x1d 0xff 0x7f 0xff 0xff
# CHECK: ljmpw *-32769(%rip)
0x66 0xff 0x2d 0xff 0x7f 0xff 0xff
# CHECK: psubsb (%rdx), %mm3
0x0f 0xe8 0x1a
# CHECK: psubsb (%rdx), %xmm3
0x66 0x0f 0xe8 0x1a
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler. Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
2015-05-14 06:44:52 +08:00
# CHECK: addq 255(%rip), %rbx
0x49, 0x03, 0x1d, 0xff, 0x00, 0x00, 0x00
# The following 4 encodings are equivalent, as confirmed by the 'xed64'
# decoder tool provided by Intel, which we assume to be canonical even
# if the real silicon does something different. If that should happen,
# then we'll all have disassembler bugs to repair.
# Try all combinations of EVEX.x and REX.b:
# CHECK: vaddps 287453952(%rip), %zmm20, %zmm15
0x62 0x11 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
# CHECK: vaddps 287453952(%rip), %zmm20, %zmm15
0x62 0x31 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
# CHECK: vaddps 287453952(%rip), %zmm20, %zmm15
0x62 0x51 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
# CHECK: vaddps 287453952(%rip), %zmm20, %zmm15
0x62 0x71 0x5c 0x40 0x58 0x3d 0x00 0x33 0x22 0x11
[X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
2017-10-22 04:03:20 +08:00
# CHECK: vaddps (%r10,%r9), %zmm20, %zmm15
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler. Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
2015-05-14 06:44:52 +08:00
0x62 0x11 0x5c 0x40 0x58 0x3c 0x0a
[X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
2017-10-22 04:03:20 +08:00
# CHECK: vaddps (%rdx,%r9), %zmm20, %zmm15
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler. Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
2015-05-14 06:44:52 +08:00
0x62 0x31 0x5c 0x40 0x58 0x3c 0x0a
[X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
2017-10-22 04:03:20 +08:00
# CHECK: vaddps (%r10,%rcx), %zmm20, %zmm15
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler. Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
2015-05-14 06:44:52 +08:00
0x62 0x51 0x5c 0x40 0x58 0x3c 0x0a
[X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
2017-10-22 04:03:20 +08:00
# CHECK: vaddps (%rdx,%rcx), %zmm20, %zmm15
[X86] Fix PR23271 - RIP-relative decoding bug in disassembler. Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
2015-05-14 06:44:52 +08:00
0x62 0x71 0x5c 0x40 0x58 0x3c 0x0a
[X86]: Correctly sign-extend 16-bit immediate in CALL instruction. Patch by Matthew Barney. Thanks! Differential Revision: http://reviews.llvm.org/D9514 llvm-svn: 240795
2015-06-27 00:58:59 +08:00
# CHECK: callq 32767
0xe8 0xff 0x7f 0x00 0x00
# CHECK: callq -32769
0xe8 0xff 0x7f 0xff 0xff
[X86][LWP] Add llvm support for LWP instructions (reapplied). This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
2017-05-03 23:51:39 +08:00
# CHECK: llwpcb %rax
0x8f 0xe9 0xf8 0x12 0xc0
# CHECK: slwpcb %rax
0x8f 0xe9 0xf8 0x12 0xc8
# CHECK: lwpins $305419896, %ebx, %rax
0x8f 0xea 0xf8 0x12 0xc3 0x78 0x56 0x34 0x12
# CHECK: lwpins $591751049, (%rsp), %rdx
0x8f 0xea 0xe8 0x12 0x04 0x24 0x89 0x67 0x45 0x23
# CHECK: lwpins $591751049, (%esp), %edx
0x67 0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23
# CHECK: lwpval $1737075661, %ebx, %rax
0x8f 0xea 0xf8 0x12 0xcb 0xcd 0xab 0x89 0x67
# CHECK: lwpval $2309737967, (%rsp), %rdx
0x8f 0xea 0xe8 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
# CHECK: lwpval $2309737967, (%esp), %edx
0x67 0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
[X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility. llvm-svn: 308818
2017-07-22 09:30:53 +08:00
# CHECK: nopq -559038737(%rbx,%rcx,8)
0x48 0x0f 0x1f 0x84 0xcb 0xef 0xbe 0xad 0xde
# CHECK: nopq %rax
0x48 0x0f 0x1f 0xC0
This patch is a result of D37262: The issues with X86 prefixes. It closes PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
2017-10-16 19:14:29 +08:00
# CHECK: xchgw %di, %ax
0x66 0x3e 0x97
Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
2017-10-23 17:36:33 +08:00
# CHECK: movq %rdx, %cs
0x4c 0x8e 0xca
This patch is a result of D37262: The issues with X86 prefixes. It closes PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
2017-10-16 19:14:29 +08:00
# CHECK: movw %bx, %cs:(%rsi,%rbp)
0x2e 0x66 0x89 0x1c 0x2e
# CHECK: movl %ebx, %cs:(%esi,%ebp)
0x2e 0x67 0x89 0x1c 0x2e
# CHECK: movl %ebx, %cs:(%rsi,%rbp)
0x2e 0x89 0x1c 0x2e
# CHECK: movw %bx, %cs:(%esi,%ebp)
0x2e 0x67 0x66 0x89 0x1c 0x2e
# CHECK: movw %bx, %cs:(%esi,%ebp)
0x2e 0x66 0x67 0x89 0x1c 0x2e