maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td

372 lines
18 KiB
TableGen
Raw Normal View History

WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
2015-07-11 02:23:10 +08:00
// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
2015-07-11 02:23:10 +08:00
//
//===----------------------------------------------------------------------===//
///
/// \file
Remove \brief commands from doxygen comments. We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
2018-05-01 23:54:18 +08:00
/// WebAssembly Memory operand code-gen constructs.
WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
2015-07-11 02:23:10 +08:00
///
//===----------------------------------------------------------------------===//
[WebAssembly] Clean up several FIXME comments. llvm-svn: 254079
2015-11-26 02:13:18 +08:00
// TODO:
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// - HasAddr64
// - WebAssemblyTargetLowering having to do with atomics
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// - Each has optional alignment.
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
// local types. These memory-only types instead zero- or sign-extend into local
// types when loading, and truncate when storing.
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// WebAssembly constant offsets are performed as unsigned with infinite
// precision, so we need to check for NoUnsignedWrap so that we don't fold an
// offset for an add that needs wrapping.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def regPlusImm : PatFrag<(ops node:$addr, node:$off),
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
(add node:$addr, node:$off),
[WebAssembly] Fix use of SDNodeFlags after API change in r301803 llvm-svn: 301811
2017-05-02 00:49:39 +08:00
[{ return N->getFlags().hasNoUnsignedWrap(); }]>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
// Treat an 'or' node as an 'add' if the or'ed bits are known to be zero.
def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
[WebAssembly] Always use the version of computeKnownBits that returns a value. NFCI. Continues the work started by @bogner in rL340594 to remove uses of the KnownBits output paramater version. llvm-svn: 349911
2018-12-21 23:25:37 +08:00
KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
[WebAssembly] Update calls to computeKnownBits after the changes from r301620. I didn't realize WebAssembly wasn't a default build target so I missed that changes were needed. llvm-svn: 301629
2017-04-28 16:15:33 +08:00
return (~Known0.Zero & ~Known1.Zero) == 0;
[WebAssembly] Teach address folding to fold bitwise-or nodes. LLVM converts adds into ors when it can prove that the operands don't share any non-zero bits. Teach address folding to recognize or instructions with constant operands with this property that can be folded into addresses as if they were adds. llvm-svn: 261562
2016-02-23 04:04:02 +08:00
}]>;
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
// GlobalAddresses are conceptually unsigned values, so we can also fold them
[WebAssembly] Disable folding of GA+reg into load/store constant offsets Summary: If the register has a negative value then unsigned overflow will occur; this case is sometimes even created intentionally by LSR. For now disable GA+reg folding. Fixes PR29127 Differential Revision: https://reviews.llvm.org/D24053 llvm-svn: 280285
2016-09-01 04:27:20 +08:00
// into immediate values as long as the add is 'nuw'.
// TODO: We'd like to also match GA offsets but there are cases where the
// register can have a negative value. Find out what more we can do.
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
def regPlusGA : PatFrag<(ops node:$addr, node:$off),
(add node:$addr, node:$off),
[{
[WebAssembly] Fix use of SDNodeFlags after API change in r301803 llvm-svn: 301811
2017-05-02 00:49:39 +08:00
return N->getFlags().hasNoUnsignedWrap();
[WebAssembly] Reorganize address offset folding. Always expect tglobaladdr and texternalsym to be wrapped in WebAssemblywrapper nodes. Also, split out a regPlusGA from regPlusImm so that it can special-case global addresses, as they can be folded in more cases. Unfortunately this doesn't enable any new optimizations yet due to SelectionDAG limitations. I'll be submitting changes to the SelectionDAG infrastructure, along with tests, in a separate patch. llvm-svn: 257394
2016-01-12 06:05:44 +08:00
}]>;
// We don't need a regPlusES because external symbols never have constant
// offsets folded into them, so we can just use add.
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
// Defines atomic and non-atomic loads, regular and extending.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
multiclass WebAssemblyLoad<WebAssemblyRegClass rc, string Name, int Opcode> {
[WebAssembly] Use named operands to identify loads and stores Summary: Uses the named operands tablegen feature to look up the indices of offset, address, and p2align operands for all load and store instructions. This replaces brittle, incorrect logic for identifying loads and store when eliminating frame indices, which previously crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59007 llvm-svn: 355770
2019-03-09 12:31:37 +08:00
let mayLoad = 1, UseNamedOperandTable = 1 in
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm "": I<(outs rc:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
(outs), (ins P2Align:$p2align, offset32_op:$off),
[], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"),
[WebAssembly] Added default stack-only instruction mode for MC. Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
2018-08-27 23:45:51 +08:00
!strconcat(Name, "\t${off}${p2align}"), Opcode>;
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
}
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Basic load.
[WebAssembly] Reorder load/store operands to match binary encoding. The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
2016-10-25 08:17:11 +08:00
// FIXME: When we can break syntax compatibility, reorder the fields in the
// asmstrings to match the binary encoding.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm LOAD_I32 : WebAssemblyLoad<I32, "i32.load", 0x28>;
defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29>;
defm LOAD_F32 : WebAssemblyLoad<F32, "f32.load", 0x2a>;
defm LOAD_F64 : WebAssemblyLoad<F64, "f64.load", 0x2b>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select loads with no constant offset.
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class LoadPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
Pat<(ty (kind I32:$addr)), (inst 0, 0, I32:$addr)>;
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatNoOffset<i32, load, LOAD_I32>;
def : LoadPatNoOffset<i64, load, LOAD_I64>;
def : LoadPatNoOffset<f32, load, LOAD_F32>;
def : LoadPatNoOffset<f64, load, LOAD_F64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select loads with a constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
// Pattern with address + immediate offset
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class LoadPatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
Pat<(ty (kind (operand I32:$addr, imm:$off))), (inst 0, imm:$off, I32:$addr)>;
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatImmOff<i32, load, regPlusImm, LOAD_I32>;
def : LoadPatImmOff<i64, load, regPlusImm, LOAD_I64>;
def : LoadPatImmOff<f32, load, regPlusImm, LOAD_F32>;
def : LoadPatImmOff<f64, load, regPlusImm, LOAD_F64>;
def : LoadPatImmOff<i32, load, or_is_add, LOAD_I32>;
def : LoadPatImmOff<i64, load, or_is_add, LOAD_I64>;
def : LoadPatImmOff<f32, load, or_is_add, LOAD_F32>;
def : LoadPatImmOff<f64, load, or_is_add, LOAD_F64>;
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class LoadPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
Pat<(ty (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)))),
[WebAssembly] Initial implementation of PIC code generation This change implements lowering of references global symbols in PIC mode. This change implements lowering of global references in PIC mode using a new @GOT reference type. @GOT references can be used with function or data symbol names combined with the get_global instruction. In this case the linker will insert the wasm global that stores the address of the symbol (either in memory for data symbols or in the wasm table for function symbols). For now I'm continuing to use the R_WASM_GLOBAL_INDEX_LEB relocation type for this type of reference which means that this relocation type can refer to either a global or a function or data symbol. We could choose to introduce specific relocation types for GOT entries in the future. See the current dynamic linking proposal: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Differential Revision: https://reviews.llvm.org/D54647 llvm-svn: 357022
2019-03-27 03:46:15 +08:00
(inst 0, tglobaladdr:$off, I32:$addr)>, Requires<[IsNotPIC]>;
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatGlobalAddr<i32, load, LOAD_I32>;
def : LoadPatGlobalAddr<i64, load, LOAD_I64>;
def : LoadPatGlobalAddr<f32, load, LOAD_F32>;
def : LoadPatGlobalAddr<f64, load, LOAD_F64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select loads with just a constant offset.
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class LoadPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
Pat<(ty (kind imm:$off)), (inst 0, imm:$off, (CONST_I32 0))>;
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatOffsetOnly<i32, load, LOAD_I32>;
def : LoadPatOffsetOnly<i64, load, LOAD_I64>;
def : LoadPatOffsetOnly<f32, load, LOAD_F32>;
def : LoadPatOffsetOnly<f64, load, LOAD_F64>;
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class LoadPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Initial implementation of PIC code generation This change implements lowering of references global symbols in PIC mode. This change implements lowering of global references in PIC mode using a new @GOT reference type. @GOT references can be used with function or data symbol names combined with the get_global instruction. In this case the linker will insert the wasm global that stores the address of the symbol (either in memory for data symbols or in the wasm table for function symbols). For now I'm continuing to use the R_WASM_GLOBAL_INDEX_LEB relocation type for this type of reference which means that this relocation type can refer to either a global or a function or data symbol. We could choose to introduce specific relocation types for GOT entries in the future. See the current dynamic linking proposal: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Differential Revision: https://reviews.llvm.org/D54647 llvm-svn: 357022
2019-03-27 03:46:15 +08:00
(inst 0, tglobaladdr:$off, (CONST_I32 0))>, Requires<[IsNotPIC]>;
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatGlobalAddrOffOnly<i32, load, LOAD_I32>;
def : LoadPatGlobalAddrOffOnly<i64, load, LOAD_I64>;
def : LoadPatGlobalAddrOffOnly<f32, load, LOAD_F32>;
def : LoadPatGlobalAddrOffOnly<f64, load, LOAD_F64>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Extending load.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm LOAD8_S_I32 : WebAssemblyLoad<I32, "i32.load8_s", 0x2c>;
defm LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.load8_u", 0x2d>;
defm LOAD16_S_I32 : WebAssemblyLoad<I32, "i32.load16_s", 0x2e>;
defm LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.load16_u", 0x2f>;
defm LOAD8_S_I64 : WebAssemblyLoad<I64, "i64.load8_s", 0x30>;
defm LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.load8_u", 0x31>;
defm LOAD16_S_I64 : WebAssemblyLoad<I64, "i64.load16_s", 0x32>;
defm LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.load16_u", 0x33>;
defm LOAD32_S_I64 : WebAssemblyLoad<I64, "i64.load32_s", 0x34>;
defm LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.load32_u", 0x35>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
// Select extending loads with no constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatNoOffset<i32, sextloadi8, LOAD8_S_I32>;
def : LoadPatNoOffset<i32, zextloadi8, LOAD8_U_I32>;
def : LoadPatNoOffset<i32, sextloadi16, LOAD16_S_I32>;
def : LoadPatNoOffset<i32, zextloadi16, LOAD16_U_I32>;
def : LoadPatNoOffset<i64, sextloadi8, LOAD8_S_I64>;
def : LoadPatNoOffset<i64, zextloadi8, LOAD8_U_I64>;
def : LoadPatNoOffset<i64, sextloadi16, LOAD16_S_I64>;
def : LoadPatNoOffset<i64, zextloadi16, LOAD16_U_I64>;
def : LoadPatNoOffset<i64, sextloadi32, LOAD32_S_I64>;
def : LoadPatNoOffset<i64, zextloadi32, LOAD32_U_I64>;
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select extending loads with a constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatImmOff<i32, sextloadi8, regPlusImm, LOAD8_S_I32>;
def : LoadPatImmOff<i32, zextloadi8, regPlusImm, LOAD8_U_I32>;
def : LoadPatImmOff<i32, sextloadi16, regPlusImm, LOAD16_S_I32>;
def : LoadPatImmOff<i32, zextloadi16, regPlusImm, LOAD16_U_I32>;
def : LoadPatImmOff<i64, sextloadi8, regPlusImm, LOAD8_S_I64>;
def : LoadPatImmOff<i64, zextloadi8, regPlusImm, LOAD8_U_I64>;
def : LoadPatImmOff<i64, sextloadi16, regPlusImm, LOAD16_S_I64>;
def : LoadPatImmOff<i64, zextloadi16, regPlusImm, LOAD16_U_I64>;
def : LoadPatImmOff<i64, sextloadi32, regPlusImm, LOAD32_S_I64>;
def : LoadPatImmOff<i64, zextloadi32, regPlusImm, LOAD32_U_I64>;
def : LoadPatImmOff<i32, sextloadi8, or_is_add, LOAD8_S_I32>;
def : LoadPatImmOff<i32, zextloadi8, or_is_add, LOAD8_U_I32>;
def : LoadPatImmOff<i32, sextloadi16, or_is_add, LOAD16_S_I32>;
def : LoadPatImmOff<i32, zextloadi16, or_is_add, LOAD16_U_I32>;
def : LoadPatImmOff<i64, sextloadi8, or_is_add, LOAD8_S_I64>;
def : LoadPatImmOff<i64, zextloadi8, or_is_add, LOAD8_U_I64>;
def : LoadPatImmOff<i64, sextloadi16, or_is_add, LOAD16_S_I64>;
def : LoadPatImmOff<i64, zextloadi16, or_is_add, LOAD16_U_I64>;
def : LoadPatImmOff<i64, sextloadi32, or_is_add, LOAD32_S_I64>;
def : LoadPatImmOff<i64, zextloadi32, or_is_add, LOAD32_U_I64>;
def : LoadPatGlobalAddr<i32, sextloadi8, LOAD8_S_I32>;
def : LoadPatGlobalAddr<i32, zextloadi8, LOAD8_U_I32>;
def : LoadPatGlobalAddr<i32, sextloadi16, LOAD16_S_I32>;
def : LoadPatGlobalAddr<i32, zextloadi8, LOAD16_U_I32>;
def : LoadPatGlobalAddr<i64, sextloadi8, LOAD8_S_I64>;
def : LoadPatGlobalAddr<i64, zextloadi8, LOAD8_U_I64>;
def : LoadPatGlobalAddr<i64, sextloadi16, LOAD16_S_I64>;
def : LoadPatGlobalAddr<i64, zextloadi16, LOAD16_U_I64>;
def : LoadPatGlobalAddr<i64, sextloadi32, LOAD32_S_I64>;
def : LoadPatGlobalAddr<i64, zextloadi32, LOAD32_U_I64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select extending loads with just a constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatOffsetOnly<i32, sextloadi8, LOAD8_S_I32>;
def : LoadPatOffsetOnly<i32, zextloadi8, LOAD8_U_I32>;
def : LoadPatOffsetOnly<i32, sextloadi16, LOAD16_S_I32>;
def : LoadPatOffsetOnly<i32, zextloadi16, LOAD16_U_I32>;
def : LoadPatOffsetOnly<i64, sextloadi8, LOAD8_S_I64>;
def : LoadPatOffsetOnly<i64, zextloadi8, LOAD8_U_I64>;
def : LoadPatOffsetOnly<i64, sextloadi16, LOAD16_S_I64>;
def : LoadPatOffsetOnly<i64, zextloadi16, LOAD16_U_I64>;
def : LoadPatOffsetOnly<i64, sextloadi32, LOAD32_S_I64>;
def : LoadPatOffsetOnly<i64, zextloadi32, LOAD32_U_I64>;
def : LoadPatGlobalAddrOffOnly<i32, sextloadi8, LOAD8_S_I32>;
def : LoadPatGlobalAddrOffOnly<i32, zextloadi8, LOAD8_U_I32>;
def : LoadPatGlobalAddrOffOnly<i32, sextloadi16, LOAD16_S_I32>;
def : LoadPatGlobalAddrOffOnly<i32, zextloadi16, LOAD16_U_I32>;
def : LoadPatGlobalAddrOffOnly<i64, sextloadi8, LOAD8_S_I64>;
def : LoadPatGlobalAddrOffOnly<i64, zextloadi8, LOAD8_U_I64>;
def : LoadPatGlobalAddrOffOnly<i64, sextloadi16, LOAD16_S_I64>;
def : LoadPatGlobalAddrOffOnly<i64, zextloadi16, LOAD16_U_I64>;
def : LoadPatGlobalAddrOffOnly<i64, sextloadi32, LOAD32_S_I64>;
def : LoadPatGlobalAddrOffOnly<i64, zextloadi32, LOAD32_U_I64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Resolve "don't care" extending loads to zero-extending loads. This is
// somewhat arbitrary, but zero-extending is conceptually simpler.
// Select "don't care" extending loads with no constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatNoOffset<i32, extloadi8, LOAD8_U_I32>;
def : LoadPatNoOffset<i32, extloadi16, LOAD16_U_I32>;
def : LoadPatNoOffset<i64, extloadi8, LOAD8_U_I64>;
def : LoadPatNoOffset<i64, extloadi16, LOAD16_U_I64>;
def : LoadPatNoOffset<i64, extloadi32, LOAD32_U_I64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select "don't care" extending loads with a constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatImmOff<i32, extloadi8, regPlusImm, LOAD8_U_I32>;
def : LoadPatImmOff<i32, extloadi16, regPlusImm, LOAD16_U_I32>;
def : LoadPatImmOff<i64, extloadi8, regPlusImm, LOAD8_U_I64>;
def : LoadPatImmOff<i64, extloadi16, regPlusImm, LOAD16_U_I64>;
def : LoadPatImmOff<i64, extloadi32, regPlusImm, LOAD32_U_I64>;
def : LoadPatImmOff<i32, extloadi8, or_is_add, LOAD8_U_I32>;
def : LoadPatImmOff<i32, extloadi16, or_is_add, LOAD16_U_I32>;
def : LoadPatImmOff<i64, extloadi8, or_is_add, LOAD8_U_I64>;
def : LoadPatImmOff<i64, extloadi16, or_is_add, LOAD16_U_I64>;
def : LoadPatImmOff<i64, extloadi32, or_is_add, LOAD32_U_I64>;
def : LoadPatGlobalAddr<i32, extloadi8, LOAD8_U_I32>;
def : LoadPatGlobalAddr<i32, extloadi16, LOAD16_U_I32>;
def : LoadPatGlobalAddr<i64, extloadi8, LOAD8_U_I64>;
def : LoadPatGlobalAddr<i64, extloadi16, LOAD16_U_I64>;
def : LoadPatGlobalAddr<i64, extloadi32, LOAD32_U_I64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select "don't care" extending loads with just a constant offset.
[WebAssembly] Refactor load ISel tablegen patterns into classes Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
2017-09-01 05:51:48 +08:00
def : LoadPatOffsetOnly<i32, extloadi8, LOAD8_U_I32>;
def : LoadPatOffsetOnly<i32, extloadi16, LOAD16_U_I32>;
def : LoadPatOffsetOnly<i64, extloadi8, LOAD8_U_I64>;
def : LoadPatOffsetOnly<i64, extloadi16, LOAD16_U_I64>;
def : LoadPatOffsetOnly<i64, extloadi32, LOAD32_U_I64>;
def : LoadPatGlobalAddrOffOnly<i32, extloadi8, LOAD8_U_I32>;
def : LoadPatGlobalAddrOffOnly<i32, extloadi16, LOAD16_U_I32>;
def : LoadPatGlobalAddrOffOnly<i64, extloadi8, LOAD8_U_I64>;
def : LoadPatGlobalAddrOffOnly<i64, extloadi16, LOAD16_U_I64>;
def : LoadPatGlobalAddrOffOnly<i64, extloadi32, LOAD32_U_I64>;
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
// Defines atomic and non-atomic stores, regular and truncating
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
multiclass WebAssemblyStore<WebAssemblyRegClass rc, string Name, int Opcode> {
[WebAssembly] Use named operands to identify loads and stores Summary: Uses the named operands tablegen feature to look up the indices of offset, address, and p2align operands for all load and store instructions. This replaces brittle, incorrect logic for identifying loads and store when eliminating frame indices, which previously crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59007 llvm-svn: 355770
2019-03-09 12:31:37 +08:00
let mayStore = 1, UseNamedOperandTable = 1 in
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm "" : I<(outs),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
(outs),
(ins P2Align:$p2align, offset32_op:$off), [],
!strconcat(Name, "\t${off}(${addr})${p2align}, $val"),
[WebAssembly] Added default stack-only instruction mode for MC. Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
2018-08-27 23:45:51 +08:00
!strconcat(Name, "\t${off}${p2align}"), Opcode>;
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
}
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Basic store.
// Note: WebAssembly inverts SelectionDAG's usual operand order.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm STORE_I32 : WebAssemblyStore<I32, "i32.store", 0x36>;
defm STORE_I64 : WebAssemblyStore<I64, "i64.store", 0x37>;
defm STORE_F32 : WebAssemblyStore<F32, "f32.store", 0x38>;
defm STORE_F64 : WebAssemblyStore<F64, "f64.store", 0x39>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select stores with no constant offset.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
class StorePatNoOffset<ValueType ty, PatFrag node, NI inst> :
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
Pat<(node ty:$val, I32:$addr), (inst 0, 0, I32:$addr, ty:$val)>;
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatNoOffset<i32, store, STORE_I32>;
def : StorePatNoOffset<i64, store, STORE_I64>;
def : StorePatNoOffset<f32, store, STORE_F32>;
def : StorePatNoOffset<f64, store, STORE_F64>;
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 08:26:39 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select stores with a constant offset.
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class StorePatImmOff<ValueType ty, PatFrag kind, PatFrag operand, NI inst> :
Pat<(kind ty:$val, (operand I32:$addr, imm:$off)),
(inst 0, imm:$off, I32:$addr, ty:$val)>;
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatImmOff<i32, store, regPlusImm, STORE_I32>;
def : StorePatImmOff<i64, store, regPlusImm, STORE_I64>;
def : StorePatImmOff<f32, store, regPlusImm, STORE_F32>;
def : StorePatImmOff<f64, store, regPlusImm, STORE_F64>;
def : StorePatImmOff<i32, store, or_is_add, STORE_I32>;
def : StorePatImmOff<i64, store, or_is_add, STORE_I64>;
def : StorePatImmOff<f32, store, or_is_add, STORE_F32>;
def : StorePatImmOff<f64, store, or_is_add, STORE_F64>;
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class StorePatGlobalAddr<ValueType ty, PatFrag kind, NI inst> :
Pat<(kind ty:$val,
(regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off))),
[WebAssembly] Initial implementation of PIC code generation This change implements lowering of references global symbols in PIC mode. This change implements lowering of global references in PIC mode using a new @GOT reference type. @GOT references can be used with function or data symbol names combined with the get_global instruction. In this case the linker will insert the wasm global that stores the address of the symbol (either in memory for data symbols or in the wasm table for function symbols). For now I'm continuing to use the R_WASM_GLOBAL_INDEX_LEB relocation type for this type of reference which means that this relocation type can refer to either a global or a function or data symbol. We could choose to introduce specific relocation types for GOT entries in the future. See the current dynamic linking proposal: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Differential Revision: https://reviews.llvm.org/D54647 llvm-svn: 357022
2019-03-27 03:46:15 +08:00
(inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>, Requires<[IsNotPIC]>;
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatGlobalAddr<i32, store, STORE_I32>;
def : StorePatGlobalAddr<i64, store, STORE_I64>;
def : StorePatGlobalAddr<f32, store, STORE_F32>;
def : StorePatGlobalAddr<f64, store, STORE_F64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select stores with just a constant offset.
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class StorePatOffsetOnly<ValueType ty, PatFrag kind, NI inst> :
Pat<(kind ty:$val, imm:$off), (inst 0, imm:$off, (CONST_I32 0), ty:$val)>;
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatOffsetOnly<i32, store, STORE_I32>;
def : StorePatOffsetOnly<i64, store, STORE_I64>;
def : StorePatOffsetOnly<f32, store, STORE_F32>;
def : StorePatOffsetOnly<f64, store, STORE_F64>;
[WebAssembly] Improve readability of load/stores and tests. NFC. Summary: - Changed variable/function names to be more consistent - Improved comments in test files - Added more tests - Fixed a few typos - Misc. cosmetic changes Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49087 llvm-svn: 336598
2018-07-10 04:18:21 +08:00
class StorePatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> :
Pat<(kind ty:$val, (WebAssemblywrapper tglobaladdr:$off)),
[WebAssembly] Initial implementation of PIC code generation This change implements lowering of references global symbols in PIC mode. This change implements lowering of global references in PIC mode using a new @GOT reference type. @GOT references can be used with function or data symbol names combined with the get_global instruction. In this case the linker will insert the wasm global that stores the address of the symbol (either in memory for data symbols or in the wasm table for function symbols). For now I'm continuing to use the R_WASM_GLOBAL_INDEX_LEB relocation type for this type of reference which means that this relocation type can refer to either a global or a function or data symbol. We could choose to introduce specific relocation types for GOT entries in the future. See the current dynamic linking proposal: https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md Differential Revision: https://reviews.llvm.org/D54647 llvm-svn: 357022
2019-03-27 03:46:15 +08:00
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>, Requires<[IsNotPIC]>;
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatGlobalAddrOffOnly<i32, store, STORE_I32>;
def : StorePatGlobalAddrOffOnly<i64, store, STORE_I64>;
def : StorePatGlobalAddrOffOnly<f32, store, STORE_F32>;
def : StorePatGlobalAddrOffOnly<f64, store, STORE_F64>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
// Truncating store.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm STORE8_I32 : WebAssemblyStore<I32, "i32.store8", 0x3a>;
defm STORE16_I32 : WebAssemblyStore<I32, "i32.store16", 0x3b>;
defm STORE8_I64 : WebAssemblyStore<I64, "i64.store8", 0x3c>;
defm STORE16_I64 : WebAssemblyStore<I64, "i64.store16", 0x3d>;
defm STORE32_I64 : WebAssemblyStore<I64, "i64.store32", 0x3e>;
[WebAssembly] Model the return value of store instructions in wasm. llvm-svn: 253916
2015-11-24 05:16:35 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select truncating stores with no constant offset.
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatNoOffset<i32, truncstorei8, STORE8_I32>;
def : StorePatNoOffset<i32, truncstorei16, STORE16_I32>;
def : StorePatNoOffset<i64, truncstorei8, STORE8_I64>;
def : StorePatNoOffset<i64, truncstorei16, STORE16_I64>;
def : StorePatNoOffset<i64, truncstorei32, STORE32_I64>;
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-09-01 06:24:11 +08:00
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select truncating stores with a constant offset.
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatImmOff<i32, truncstorei8, regPlusImm, STORE8_I32>;
def : StorePatImmOff<i32, truncstorei16, regPlusImm, STORE16_I32>;
def : StorePatImmOff<i64, truncstorei8, regPlusImm, STORE8_I64>;
def : StorePatImmOff<i64, truncstorei16, regPlusImm, STORE16_I64>;
def : StorePatImmOff<i64, truncstorei32, regPlusImm, STORE32_I64>;
def : StorePatImmOff<i32, truncstorei8, or_is_add, STORE8_I32>;
def : StorePatImmOff<i32, truncstorei16, or_is_add, STORE16_I32>;
def : StorePatImmOff<i64, truncstorei8, or_is_add, STORE8_I64>;
def : StorePatImmOff<i64, truncstorei16, or_is_add, STORE16_I64>;
def : StorePatImmOff<i64, truncstorei32, or_is_add, STORE32_I64>;
def : StorePatGlobalAddr<i32, truncstorei8, STORE8_I32>;
def : StorePatGlobalAddr<i32, truncstorei16, STORE16_I32>;
def : StorePatGlobalAddr<i64, truncstorei8, STORE8_I64>;
def : StorePatGlobalAddr<i64, truncstorei16, STORE16_I64>;
def : StorePatGlobalAddr<i64, truncstorei32, STORE32_I64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
// Select truncating stores with just a constant offset.
[WebAssembly] Refactor tablegen for store instructions (NFC) Summary: Add patterns similar to loads. Differential Revision: https://reviews.llvm.org/D45064 llvm-svn: 328876
2018-03-31 01:02:50 +08:00
def : StorePatOffsetOnly<i32, truncstorei8, STORE8_I32>;
def : StorePatOffsetOnly<i32, truncstorei16, STORE16_I32>;
def : StorePatOffsetOnly<i64, truncstorei8, STORE8_I64>;
def : StorePatOffsetOnly<i64, truncstorei16, STORE16_I64>;
def : StorePatOffsetOnly<i64, truncstorei32, STORE32_I64>;
def : StorePatGlobalAddrOffOnly<i32, truncstorei8, STORE8_I32>;
def : StorePatGlobalAddrOffOnly<i32, truncstorei16, STORE16_I32>;
def : StorePatGlobalAddrOffOnly<i64, truncstorei8, STORE8_I64>;
def : StorePatGlobalAddrOffOnly<i64, truncstorei16, STORE16_I64>;
def : StorePatGlobalAddrOffOnly<i64, truncstorei32, STORE32_I64>;
[WebAssembly] Implement instruction selection for constant offsets in addresses. Add instruction patterns for matching load and store instructions with constant offsets in addresses. The code is fairly redundant due to the need to replicate everything between imm, tglobaldadr, and texternalsym, but this appears to be common tablegen practice. The main alternative appears to be to introduce matching functions with C++ code, but sticking with purely generated matchers seems better for now. Also note that this doesn't yet support offsets from getelementptr, which will be the most common case; that will depend on a change in target-independent code in order to set the NoUnsignedWrap flag, which I'll submit separately. Until then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add. Also implement isLegalAddressingMode with an approximation of this. Differential Revision: http://reviews.llvm.org/D15538 llvm-svn: 255681
2015-12-16 06:01:29 +08:00
[WebAssembly] Rename memory_size intrinsic to current_memory This follows the recent renaming in the wasm spec. llvm-svn: 268255
2016-05-03 01:25:22 +08:00
// Current memory size.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins i32imm:$flags),
(outs), (ins i32imm:$flags),
[(set I32:$dst,
(int_wasm_memory_size (i32 imm:$flags)))],
"memory.size\t$dst, $flags", "memory.size\t$flags",
0x3f>,
Requires<[HasAddr32]>;
[WebAssembly] Add a resize_memory intrinsic. llvm-svn: 249178
2015-10-03 04:10:26 +08:00
[WebAssembly] Update wasm builtin functions to match spec changes. The page_size operator has been removed from the spec, and the resize_memory operator has been changed to grow_memory. llvm-svn: 252202
2015-11-06 04:16:59 +08:00
// Grow memory.
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
defm MEMORY_GROW_I32 : I<(outs I32:$dst), (ins i32imm:$flags, I32:$delta),
[WebAssembly] Added default stack-only instruction mode for MC. Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
2018-08-27 23:45:51 +08:00
(outs), (ins i32imm:$flags),
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
[(set I32:$dst,
(int_wasm_memory_grow (i32 imm:$flags),
I32:$delta))],
"memory.grow\t$dst, $flags, $delta",
[WebAssembly] Added default stack-only instruction mode for MC. Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
2018-08-27 23:45:51 +08:00
"memory.grow\t$flags", 0x40>,
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
Requires<[HasAddr32]>;