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llvm-project/llvm/test/CodeGen/Mips/lcb4a.ll

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[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
2015-10-15 22:34:23 +08:00
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci
final patch for very long conditional branches for mips16 constant islands. this completes the basic port of ARM constant islands to Mips16. More testing, code review, cleanup is in order but basically everything seems to be working. A bug in gas is preventing some of the runtime testing but I hope to resolve this soon. llvm-svn: 196331
2013-12-04 07:42:51 +08:00
@i = global i32 0, align 4
@j = common global i32 0, align 4
@k = common global i32 0, align 4
; Function Attrs: nounwind optsize
define i32 @foo() #0 {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @i, align 4, !tbaa !1
final patch for very long conditional branches for mips16 constant islands. this completes the basic port of ARM constant islands to Mips16. More testing, code review, cleanup is in order but basically everything seems to be working. A bug in gas is preventing some of the runtime testing but I hope to resolve this soon. llvm-svn: 196331
2013-12-04 07:42:51 +08:00
%cmp = icmp eq i32 %0, 0
br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry
tail call void asm sideeffect ".space 1000", ""() #1, !srcloc !5
br label %if.end
if.else: ; preds = %entry
tail call void asm sideeffect ".space 1004", ""() #1, !srcloc !6
br label %if.end
if.end: ; preds = %if.else, %if.then
%storemerge = phi i32 [ 1, %if.else ], [ 0, %if.then ]
store i32 %storemerge, i32* @i, align 4, !tbaa !1
ret i32 0
}
; ci: beqz $3, $BB0_2
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ci: # %bb.1: # %if.else
final patch for very long conditional branches for mips16 constant islands. this completes the basic port of ARM constant islands to Mips16. More testing, code review, cleanup is in order but basically everything seems to be working. A bug in gas is preventing some of the runtime testing but I hope to resolve this soon. llvm-svn: 196331
2013-12-04 07:42:51 +08:00
; Function Attrs: nounwind optsize
define i32 @goo() #0 {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @i, align 4, !tbaa !1
final patch for very long conditional branches for mips16 constant islands. this completes the basic port of ARM constant islands to Mips16. More testing, code review, cleanup is in order but basically everything seems to be working. A bug in gas is preventing some of the runtime testing but I hope to resolve this soon. llvm-svn: 196331
2013-12-04 07:42:51 +08:00
%cmp = icmp eq i32 %0, 0
br i1 %cmp, label %if.then, label %if.else
if.then: ; preds = %entry
tail call void asm sideeffect ".space 1000000", ""() #1, !srcloc !7
br label %if.end
if.else: ; preds = %entry
tail call void asm sideeffect ".space 1000004", ""() #1, !srcloc !8
br label %if.end
if.end: ; preds = %if.else, %if.then
%storemerge = phi i32 [ 1, %if.else ], [ 0, %if.then ]
store i32 %storemerge, i32* @i, align 4, !tbaa !1
ret i32 0
}
; ci: bnez $3, $BB1_1 # 16 bit inst
; ci: jal $BB1_2 # branch
; ci: nop
; ci: $BB1_1: # %if.else
attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
IR: Make metadata typeless in assembly Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
2014-12-16 03:07:53 +08:00
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}
!5 = !{i32 58}
!6 = !{i32 108}
!7 = !{i32 190}
!8 = !{i32 243}