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llvm-project/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll

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[mips] Use --check-prefixes where appropriate. NFC. llvm-svn: 273669
2016-06-24 20:23:17 +08:00
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL
; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
[mips] Add support for mfhc1 and mthc1. llvm-svn: 188848
2013-08-21 07:47:25 +08:00
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
2011-04-16 03:52:08 +08:00
@a = external global i32
[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
2014-07-14 20:41:31 +08:00
; ALL-LABEL: f:
; NO-MFHC1: mtc1
; NO-MFHC1: mtc1
; HAS-MFHC1-DAG: mtc1
; HAS-MFHC1-DAG: mthc1
[mips] Add support for mfhc1 and mthc1. llvm-svn: 188848
2013-08-21 07:47:25 +08:00
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
2011-04-16 03:52:08 +08:00
define double @f(i32 %a1, double %d) nounwind {
entry:
store i32 %a1, i32* @a, align 4
%add = fadd double %d, 2.000000e+00
ret double %add
}
[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
2014-07-14 20:41:31 +08:00
; ALL-LABEL: f3:
; NO-MFHC1: mfc1
; NO-MFHC1: mfc1
; HAS-MFHC1-DAG: mfc1
; HAS-MFHC1-DAG: mfhc1
[mips] Add support for mfhc1 and mthc1. llvm-svn: 188848
2013-08-21 07:47:25 +08:00
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
2011-04-16 03:52:08 +08:00
define void @f3(double %d, i32 %a1) nounwind {
entry:
tail call void @f2(i32 %a1, double %d) nounwind
ret void
}
declare void @f2(i32, double)