AMDGPU: Add new amdgcn.init.exec intrinsics
v2: More tests, bug fixes, cosmetic changes.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D31762
llvm-svn: 301677
2017-04-29 04:21:58 +08:00
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;RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GCN
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; GCN-LABEL: {{^}}full_mask:
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; GCN: s_mov_b64 exec, -1
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; GCN: v_add_f32_e32 v0,
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define amdgpu_ps float @full_mask(float %a, float %b) {
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main_body:
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%s = fadd float %a, %b
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call void @llvm.amdgcn.init.exec(i64 -1)
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ret float %s
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}
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; GCN-LABEL: {{^}}partial_mask:
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; GCN: s_mov_b64 exec, 0x1e240
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; GCN: v_add_f32_e32 v0,
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define amdgpu_ps float @partial_mask(float %a, float %b) {
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main_body:
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%s = fadd float %a, %b
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call void @llvm.amdgcn.init.exec(i64 123456)
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ret float %s
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}
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; GCN-LABEL: {{^}}input_s3off8:
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; GCN: s_bfe_u32 s0, s3, 0x70008
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; GCN: s_bfm_b64 exec, s0, 0
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; GCN: s_cmp_eq_u32 s0, 64
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; GCN: s_cmov_b64 exec, -1
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; GCN: v_add_f32_e32 v0,
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define amdgpu_ps float @input_s3off8(i32 inreg, i32 inreg, i32 inreg, i32 inreg %count, float %a, float %b) {
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main_body:
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%s = fadd float %a, %b
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call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8)
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ret float %s
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}
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; GCN-LABEL: {{^}}input_s0off19:
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; GCN: s_bfe_u32 s0, s0, 0x70013
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; GCN: s_bfm_b64 exec, s0, 0
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; GCN: s_cmp_eq_u32 s0, 64
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; GCN: s_cmov_b64 exec, -1
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; GCN: v_add_f32_e32 v0,
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define amdgpu_ps float @input_s0off19(i32 inreg %count, float %a, float %b) {
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main_body:
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%s = fadd float %a, %b
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call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19)
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ret float %s
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}
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; GCN-LABEL: {{^}}reuse_input:
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; GCN: s_bfe_u32 s1, s0, 0x70013
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; GCN: s_bfm_b64 exec, s1, 0
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; GCN: s_cmp_eq_u32 s1, 64
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; GCN: s_cmov_b64 exec, -1
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2017-12-01 06:51:26 +08:00
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; GCN: v_add_u32_e32 v0, s0, v0
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AMDGPU: Add new amdgcn.init.exec intrinsics
v2: More tests, bug fixes, cosmetic changes.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D31762
llvm-svn: 301677
2017-04-29 04:21:58 +08:00
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define amdgpu_ps float @reuse_input(i32 inreg %count, i32 %a) {
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main_body:
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call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19)
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%s = add i32 %a, %count
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%f = sitofp i32 %s to float
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ret float %f
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}
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; GCN-LABEL: {{^}}reuse_input2:
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; GCN: s_bfe_u32 s1, s0, 0x70013
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; GCN: s_bfm_b64 exec, s1, 0
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; GCN: s_cmp_eq_u32 s1, 64
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; GCN: s_cmov_b64 exec, -1
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2017-12-01 06:51:26 +08:00
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; GCN: v_add_u32_e32 v0, s0, v0
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AMDGPU: Add new amdgcn.init.exec intrinsics
v2: More tests, bug fixes, cosmetic changes.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D31762
llvm-svn: 301677
2017-04-29 04:21:58 +08:00
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define amdgpu_ps float @reuse_input2(i32 inreg %count, i32 %a) {
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main_body:
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%s = add i32 %a, %count
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%f = sitofp i32 %s to float
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call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19)
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ret float %f
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}
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declare void @llvm.amdgcn.init.exec(i64) #1
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declare void @llvm.amdgcn.init.exec.from.input(i32, i32) #1
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attributes #1 = { convergent }
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