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llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

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[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
///
/// \file
Remove \brief commands from doxygen comments. We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
2018-05-01 23:54:18 +08:00
/// This file provides WebAssembly-specific target descriptions.
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
Move Object format code to lib/BinaryFormat. This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
2017-06-07 11:48:56 +08:00
#include "llvm/BinaryFormat/Wasm.h"
[WebAssembly] Define OperandTypes for decoding immediate values. llvm-svn: 257438
2016-01-12 11:09:16 +08:00
#include "llvm/MC/MCInstrDesc.h"
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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#include "llvm/Support/DataTypes.h"
[WebAssembly] Update MCObjectWriter and associated interfaces after r315327 llvm-svn: 315335
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#include <memory>
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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namespace llvm {
class MCAsmBackend;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
MC: Separate creating a generic object writer from creating a target object writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
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class MCObjectTargetWriter;
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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class MCSubtargetInfo;
[WebAssembly] Implement more WebAssembly binary encoding. This changes locals from being declared by the emitLocal hook in WebAssemblyTargetStreamer, rather than with an instruction. After exploring the infastructure in LLVM more, this seems to make more sense since declaring locals doesn't use an encoded opcode. This also adds more 0xd opcodes, type encodings, and miscellaneous binary encoding bits. llvm-svn: 285040
2016-10-25 07:27:49 +08:00
class MVT;
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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class Target;
class Triple;
[WebAssembly] Emit .param, .result, and .local through MC. This eliminates one of the main remaining uses of EmitRawText. llvm-svn: 253878
2015-11-24 00:50:18 +08:00
class raw_pwrite_stream;
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
Move the global variables representing each Target behind accessor function This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
2016-10-10 07:00:34 +08:00
Target &getTheWebAssemblyTarget32();
Target &getTheWebAssemblyTarget64();
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
[WebAssembly] Use __stack_pointer global when writing wasm binary This ensures that symbolic relocations are generated for stack pointer manipulations. These relocations are of type R_WEBASSEMBLY_GLOBAL_INDEX_LEB. This change also adds support for reading relocations of this type in WasmObjectFile.cpp. Since its a globally imported symbol this does mean that the get_global/set_global instruction won't be valid until the objects are linked that global used in no longer an imported global. Differential Revision: https://reviews.llvm.org/D34172 llvm-svn: 305616
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MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
[WebAssembly] Emit .param, .result, and .local through MC. This eliminates one of the main remaining uses of EmitRawText. llvm-svn: 253878
2015-11-24 00:50:18 +08:00
[WebAssembly] Remove unused arguments, unused functions. NFC. llvm-svn: 257125
2016-01-08 08:43:54 +08:00
MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
MC: Separate creating a generic object writer from creating a target object writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
2018-05-22 03:20:29 +08:00
std::unique_ptr<MCObjectTargetWriter>
createWebAssemblyWasmObjectWriter(bool Is64Bit);
[WebAssembly] Add skeleton MC support for the Wasm container format This just adds the basic skeleton for supporting a new object file format. All of the actual encoding will be implemented in followup patches. Differential Revision: https://reviews.llvm.org/D26722 llvm-svn: 295803
2017-02-22 09:23:18 +08:00
[WebAssembly] Define OperandTypes for decoding immediate values. llvm-svn: 257438
2016-01-12 11:09:16 +08:00
namespace WebAssembly {
enum OperandType {
/// Basic block label in a branch construct.
OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
[WebAssembly] Add an option to make get_local/set_local explicit. This patch adds a pass, controlled by an option and off by default for now, for making implicit get_local/set_local explicit. This simplifies emitting wasm with MC. Differential Revision: https://reviews.llvm.org/D25836 llvm-svn: 285009
2016-10-25 03:49:43 +08:00
/// Local index.
OPERAND_LOCAL,
[WebAssembly] Add instruction definitions for drop and get/set_global. llvm-svn: 293922
2017-02-03 03:29:44 +08:00
/// Global index.
OPERAND_GLOBAL,
[WebAssembly] Add binary-encoding opcode values to instruction descriptions. llvm-svn: 283389
2016-10-06 05:24:08 +08:00
/// 32-bit integer immediates.
OPERAND_I32IMM,
/// 64-bit integer immediates.
OPERAND_I64IMM,
[WebAssembly] Implement support for custom NaN bit patterns. llvm-svn: 260968
2016-02-16 23:14:23 +08:00
/// 32-bit floating-point immediates.
[WebAssembly] Rename OPERAND_FP32IMM to OPERAND_F32IMM. WebAssembly documentation consistently says "f32" rather than "fp32" to describe 32-bit floating-point. llvm-svn: 283146
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OPERAND_F32IMM,
[WebAssembly] Implement support for custom NaN bit patterns. llvm-svn: 260968
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/// 64-bit floating-point immediates.
[WebAssembly] Rename OPERAND_FP32IMM to OPERAND_F32IMM. WebAssembly documentation consistently says "f32" rather than "fp32" to describe 32-bit floating-point. llvm-svn: 283146
2016-10-04 05:31:31 +08:00
OPERAND_F64IMM,
[WebAssembly] v128.const Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
2018-08-22 05:03:18 +08:00
/// 8-bit vector lane immediate
OPERAND_VEC_I8IMM,
/// 16-bit vector lane immediate
OPERAND_VEC_I16IMM,
/// 32-bit vector lane immediate
OPERAND_VEC_I32IMM,
/// 64-bit vector lane immediate
OPERAND_VEC_I64IMM,
[WebAssembly] Annotate call and load/store immediates. These will be used to guide the binary encoding of these immediates. llvm-svn: 290412
2016-12-23 11:23:52 +08:00
/// 32-bit unsigned function indices.
OPERAND_FUNCTION32,
/// 32-bit unsigned memory offsets.
OPERAND_OFFSET32,
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
/// p2align immediate for load and store address alignment.
[WebAssemby] Implement block signatures. Per spec changes, this implements block signatures, and adds just enough logic to produce correct block signatures at the ends of functions. Differential Revision: https://reviews.llvm.org/D25144 llvm-svn: 283503
2016-10-07 06:29:32 +08:00
OPERAND_P2ALIGN,
/// signature immediate for block/loop.
[WebAssembly] Basic support for Wasm object file encoding. With the "wasm32-unknown-unknown-wasm" triple, this allows writing out simple wasm object files, and is another step in a larger series toward migrating from ELF to general wasm object support. Note that this code and the binary format itself is still experimental. llvm-svn: 296190
2017-02-25 07:18:00 +08:00
OPERAND_SIGNATURE,
/// type signature immediate for call_indirect.
OPERAND_TYPEINDEX,
[WebAssembly] Define OperandTypes for decoding immediate values. llvm-svn: 257438
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};
} // end namespace WebAssembly
namespace WebAssemblyII {
enum {
// For variadic instructions, this flag indicates whether an operand
// in the variable_ops range is an immediate value.
[WebAssembly] Introduce a WebAssemblyTargetStreamer class. Refactor .param, .result, .local, and .endfunc, as directives, using the proper MCTargetStreamer mechanism, rather than fake instructions. llvm-svn: 257511
2016-01-13 04:30:51 +08:00
VariableOpIsImmediate = (1 << 0),
[WebAssembly] Make CFG stackification independent of basic-block labels. This patch changes the way labels are referenced. Instead of referencing the basic-block label name (eg. .LBB0_0), instructions now just have an immediate which indicates the depth in the control-flow stack to find a label to jump to. This makes them much closer to what we expect to have in the binary encoding, and avoids the problem of basic-block label names not being explicit in the binary encoding. Also, it terminates blocks and loops with end_block and end_loop instructions, rather than basic-block label names, for similar reasons. This will also fix problems where two constructs appear to have the same label, because we no longer explicitly use labels, so consumers that need labels will presumably create their own labels, and presumably they won't reuse labels when they do. This patch does make the code a little more awkward to read; as a partial mitigation, this patch also introduces comments showing where the labels are, and comments on each branch showing where it's branching to. llvm-svn: 257505
2016-01-13 03:14:46 +08:00
// For immediate values in the variable_ops range, this flag indicates
// whether the value represents a control-flow label.
[WebAssembly] Implement more WebAssembly binary encoding. This changes locals from being declared by the emitLocal hook in WebAssemblyTargetStreamer, rather than with an instruction. After exploring the infastructure in LLVM more, this seems to make more sense since declaring locals doesn't use an encoded opcode. This also adds more 0xd opcodes, type encodings, and miscellaneous binary encoding bits. llvm-svn: 285040
2016-10-25 07:27:49 +08:00
VariableOpImmediateIsLabel = (1 << 1)
[WebAssembly] Define OperandTypes for decoding immediate values. llvm-svn: 257438
2016-01-12 11:09:16 +08:00
};
[WebAssembly] Cleanup of the way globals and global flags are handled Differential Revision: https://reviews.llvm.org/D44030 llvm-svn: 338894
2018-08-03 22:33:37 +08:00
/// Target Operand Flag enum.
enum TOF {
MO_NO_FLAG = 0,
// Flags to indicate the type of the symbol being referenced
MO_SYMBOL_FUNCTION = 0x1,
MO_SYMBOL_GLOBAL = 0x2,
MO_SYMBOL_MASK = 0x3,
};
[WebAssembly] Define OperandTypes for decoding immediate values. llvm-svn: 257438
2016-01-12 11:09:16 +08:00
} // end namespace WebAssemblyII
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
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} // end namespace llvm
// Defines symbolic names for WebAssembly registers. This defines a mapping from
// register name to register number.
//
WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
2015-07-11 02:23:10 +08:00
#define GET_REGINFO_ENUM
#include "WebAssemblyGenRegisterInfo.inc"
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
// Defines symbolic names for the WebAssembly instructions.
//
#define GET_INSTRINFO_ENUM
#include "WebAssemblyGenInstrInfo.inc"
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
#define GET_SUBTARGETINFO_ENUM
#include "WebAssemblyGenSubtargetInfo.inc"
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
namespace llvm {
namespace WebAssembly {
/// Return the default p2align value for a load or store with the given opcode.
inline unsigned GetDefaultP2Align(unsigned Opcode) {
switch (Opcode) {
case WebAssembly::LOAD8_S_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD8_S_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD8_U_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD8_U_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD8_S_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD8_S_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD8_U_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD8_U_I64_S:
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
case WebAssembly::ATOMIC_LOAD8_U_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD8_U_I32_S:
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
case WebAssembly::ATOMIC_LOAD8_U_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD8_U_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE8_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE8_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE8_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE8_I64_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE8_I32:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE8_I32_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE8_I64:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE8_I64_S:
[WebAssembly] Support for binary atomic RMW instructions Summary: This adds support for binary atomic read-modify-write instructions: add, sub, and, or, xor, and xchg. This does not yet support translations of some of LLVM IR atomicrmw instructions (nand, max, min, umax, and umin) that do not have a direct counterpart in wasm instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49088 llvm-svn: 336615
2018-07-10 06:30:51 +08:00
case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
case WebAssembly::ATOMIC_RMW8_U_AND_I32:
case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
case WebAssembly::ATOMIC_RMW8_U_AND_I64:
case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
case WebAssembly::ATOMIC_RMW8_U_OR_I32:
case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
case WebAssembly::ATOMIC_RMW8_U_OR_I64:
case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
[WebAssembly] Support for a ternary atomic RMW instruction Summary: This adds support for a ternary atomic RMW instruction: cmpxchg. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49195 llvm-svn: 338617
2018-08-02 03:40:28 +08:00
case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
return 0;
case WebAssembly::LOAD16_S_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD16_S_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD16_U_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD16_U_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD16_S_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD16_S_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD16_U_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD16_U_I64_S:
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
case WebAssembly::ATOMIC_LOAD16_U_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD16_U_I32_S:
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
case WebAssembly::ATOMIC_LOAD16_U_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD16_U_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE16_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE16_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE16_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE16_I64_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE16_I32:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE16_I32_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE16_I64:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE16_I64_S:
[WebAssembly] Support for binary atomic RMW instructions Summary: This adds support for binary atomic read-modify-write instructions: add, sub, and, or, xor, and xchg. This does not yet support translations of some of LLVM IR atomicrmw instructions (nand, max, min, umax, and umin) that do not have a direct counterpart in wasm instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49088 llvm-svn: 336615
2018-07-10 06:30:51 +08:00
case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
case WebAssembly::ATOMIC_RMW16_U_AND_I32:
case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
case WebAssembly::ATOMIC_RMW16_U_AND_I64:
case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
case WebAssembly::ATOMIC_RMW16_U_OR_I32:
case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
case WebAssembly::ATOMIC_RMW16_U_OR_I64:
case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
[WebAssembly] Support for a ternary atomic RMW instruction Summary: This adds support for a ternary atomic RMW instruction: cmpxchg. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49195 llvm-svn: 338617
2018-08-02 03:40:28 +08:00
case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
return 1;
case WebAssembly::LOAD_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD_F32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD_F32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE_F32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE_F32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD32_S_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD32_S_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD32_U_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD32_U_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE32_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE32_I64_S:
[WebAssembly] Add target feature for atomics Summary: This tracks the WebAssembly threads feature proposal at https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md Differential Revision: https://reviews.llvm.org/D37300 llvm-svn: 312145
2017-08-31 02:07:45 +08:00
case WebAssembly::ATOMIC_LOAD_I32:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD_I32_S:
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
case WebAssembly::ATOMIC_LOAD32_U_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD32_U_I64_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE_I32:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE_I32_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE32_I64:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE32_I64_S:
[WebAssembly] Support for binary atomic RMW instructions Summary: This adds support for binary atomic read-modify-write instructions: add, sub, and, or, xor, and xchg. This does not yet support translations of some of LLVM IR atomicrmw instructions (nand, max, min, umax, and umin) that do not have a direct counterpart in wasm instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49088 llvm-svn: 336615
2018-07-10 06:30:51 +08:00
case WebAssembly::ATOMIC_RMW_ADD_I32:
case WebAssembly::ATOMIC_RMW_ADD_I32_S:
case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
case WebAssembly::ATOMIC_RMW_SUB_I32:
case WebAssembly::ATOMIC_RMW_SUB_I32_S:
case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
case WebAssembly::ATOMIC_RMW_AND_I32:
case WebAssembly::ATOMIC_RMW_AND_I32_S:
case WebAssembly::ATOMIC_RMW32_U_AND_I64:
case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
case WebAssembly::ATOMIC_RMW_OR_I32:
case WebAssembly::ATOMIC_RMW_OR_I32_S:
case WebAssembly::ATOMIC_RMW32_U_OR_I64:
case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
case WebAssembly::ATOMIC_RMW_XOR_I32:
case WebAssembly::ATOMIC_RMW_XOR_I32_S:
case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
case WebAssembly::ATOMIC_RMW_XCHG_I32:
case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
[WebAssembly] Support for a ternary atomic RMW instruction Summary: This adds support for a ternary atomic RMW instruction: cmpxchg. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49195 llvm-svn: 338617
2018-08-02 03:40:28 +08:00
case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
[WebAssembly] Support for atomic.wait / atomic.wake instructions Summary: This adds support for atomic.wait / atomic.wake instructions in the wasm thread proposal. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49395 llvm-svn: 338770
2018-08-03 05:44:24 +08:00
case WebAssembly::ATOMIC_NOTIFY:
case WebAssembly::ATOMIC_NOTIFY_S:
case WebAssembly::ATOMIC_WAIT_I32:
case WebAssembly::ATOMIC_WAIT_I32_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
return 2;
case WebAssembly::LOAD_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::LOAD_F64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::LOAD_F64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
case WebAssembly::STORE_F64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::STORE_F64_S:
[WebAssembly] Add the rest of the atomic loads Add extending loads and constant offset patterns A bit more refactoring of the tablegen to make the patterns fairly nice and uniform between the regular and atomic loads. Differential Revision: https://reviews.llvm.org/D38523 llvm-svn: 315022
2017-10-06 05:18:42 +08:00
case WebAssembly::ATOMIC_LOAD_I64:
[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets. Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
2018-06-19 05:22:44 +08:00
case WebAssembly::ATOMIC_LOAD_I64_S:
[WebAssembly] Support for atomic stores Summary: Add support for atomic store instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48839 llvm-svn: 336145
2018-07-03 05:22:59 +08:00
case WebAssembly::ATOMIC_STORE_I64:
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter Summary: This was missing in D48839 (rL336145). Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D48992 llvm-svn: 336390
2018-07-06 05:27:09 +08:00
case WebAssembly::ATOMIC_STORE_I64_S:
[WebAssembly] Support for binary atomic RMW instructions Summary: This adds support for binary atomic read-modify-write instructions: add, sub, and, or, xor, and xchg. This does not yet support translations of some of LLVM IR atomicrmw instructions (nand, max, min, umax, and umin) that do not have a direct counterpart in wasm instructions. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49088 llvm-svn: 336615
2018-07-10 06:30:51 +08:00
case WebAssembly::ATOMIC_RMW_ADD_I64:
case WebAssembly::ATOMIC_RMW_ADD_I64_S:
case WebAssembly::ATOMIC_RMW_SUB_I64:
case WebAssembly::ATOMIC_RMW_SUB_I64_S:
case WebAssembly::ATOMIC_RMW_AND_I64:
case WebAssembly::ATOMIC_RMW_AND_I64_S:
case WebAssembly::ATOMIC_RMW_OR_I64:
case WebAssembly::ATOMIC_RMW_OR_I64_S:
case WebAssembly::ATOMIC_RMW_XOR_I64:
case WebAssembly::ATOMIC_RMW_XOR_I64_S:
case WebAssembly::ATOMIC_RMW_XCHG_I64:
case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
[WebAssembly] Support for a ternary atomic RMW instruction Summary: This adds support for a ternary atomic RMW instruction: cmpxchg. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49195 llvm-svn: 338617
2018-08-02 03:40:28 +08:00
case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
[WebAssembly] Support for atomic.wait / atomic.wake instructions Summary: This adds support for atomic.wait / atomic.wake instructions in the wasm thread proposal. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49395 llvm-svn: 338770
2018-08-03 05:44:24 +08:00
case WebAssembly::ATOMIC_WAIT_I64:
case WebAssembly::ATOMIC_WAIT_I64_S:
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
return 3;
[WebAssembly] SIMD loads and stores Summary: Reuse the patterns from WebAssemblyInstrMemory.td. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51383 llvm-svn: 341127
2018-08-31 05:36:48 +08:00
case WebAssembly::LOAD_v16i8:
case WebAssembly::LOAD_v16i8_S:
case WebAssembly::LOAD_v8i16:
case WebAssembly::LOAD_v8i16_S:
case WebAssembly::LOAD_v4i32:
case WebAssembly::LOAD_v4i32_S:
case WebAssembly::LOAD_v2i64:
case WebAssembly::LOAD_v2i64_S:
case WebAssembly::LOAD_v4f32:
case WebAssembly::LOAD_v4f32_S:
case WebAssembly::LOAD_v2f64:
case WebAssembly::LOAD_v2f64_S:
case WebAssembly::STORE_v16i8:
case WebAssembly::STORE_v16i8_S:
case WebAssembly::STORE_v8i16:
case WebAssembly::STORE_v8i16_S:
case WebAssembly::STORE_v4i32:
case WebAssembly::STORE_v4i32_S:
case WebAssembly::STORE_v2i64:
case WebAssembly::STORE_v2i64_S:
case WebAssembly::STORE_v4f32:
case WebAssembly::STORE_v4f32_S:
case WebAssembly::STORE_v2f64:
case WebAssembly::STORE_v2f64_S:
return 4;
[WebAssembly] Support CFI for WebAssembly target Summary: This patch implements CFI for WebAssembly. It modifies the LowerTypeTest pass to pre-assign table indexes to functions that are called indirectly, and lowers type checks to test against the appropriate table indexes. It also modifies the WebAssembly backend to support a special ".indidx" assembly directive that propagates the table index assignments out to the linker. Patch by Dominic Chen Differential Revision: https://reviews.llvm.org/D21768 llvm-svn: 277398
2016-08-02 06:25:02 +08:00
default:
llvm_unreachable("Only loads and stores have p2align values");
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
}
}
[WebAssembly] Fix uses of FrameIndex as store values Previously the code assumed all uses of FI on loads and stores were as addresses. This checks whether the use is the address or a value and handles the latter case as it does for non-memory instructions. llvm-svn: 259306
2016-01-31 05:43:08 +08:00
/// The operand number of the load or store address in load/store instructions.
[WebAssembly] Reorder load/store operands to match binary encoding. The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
2016-10-25 08:17:11 +08:00
static const unsigned LoadAddressOperandNo = 3;
static const unsigned StoreAddressOperandNo = 2;
[WebAssembly] Remove the output operand from stores. Per spec changes, store instructions in WebAssembly no longer have a return value. Update the instruction descriptions. Differential Revision: https://reviews.llvm.org/D25122 llvm-svn: 283501
2016-10-07 06:08:28 +08:00
/// The operand number of the load or store p2align in load/store instructions.
[WebAssembly] Reorder load/store operands to match binary encoding. The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
2016-10-25 08:17:11 +08:00
static const unsigned LoadP2AlignOperandNo = 1;
static const unsigned StoreP2AlignOperandNo = 0;
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
[WebAssemby] Implement block signatures. Per spec changes, this implements block signatures, and adds just enough logic to produce correct block signatures at the ends of functions. Differential Revision: https://reviews.llvm.org/D25144 llvm-svn: 283503
2016-10-07 06:29:32 +08:00
/// This is used to indicate block signatures.
Reland "[WebAssembly] More uses of uint8_t for single byte values" Summary: Original change was D43991 (rL326541) and was reverted by rL326571 and rL326572. This adds also the necessary MCCodeEmitter patch. Reviewers: sbc100 Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits, ncw Differential Revision: https://reviews.llvm.org/D44034 llvm-svn: 326614
2018-03-03 04:52:59 +08:00
enum class ExprType : unsigned {
[WebAssembly] Replace SIMD expression types with V128 Summary: The spec only defines a SIMD expression type of V128 and leaves interpretation of different vector types to the instructions. Differential Revision: https://reviews.llvm.org/D50367 Patch by Thomas Lively llvm-svn: 339082
2018-08-07 07:16:50 +08:00
Void = 0x40,
I32 = 0x7F,
I64 = 0x7E,
F32 = 0x7D,
F64 = 0x7C,
V128 = 0x7B,
[WebAssembly] Add except_ref as a first-class type Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 llvm-svn: 326985
2018-03-08 12:05:37 +08:00
ExceptRef = 0x68
[WebAssembly] Add an option to make get_local/set_local explicit. This patch adds a pass, controlled by an option and off by default for now, for making implicit get_local/set_local explicit. This simplifies emitting wasm with MC. Differential Revision: https://reviews.llvm.org/D25836 llvm-svn: 285009
2016-10-25 03:49:43 +08:00
};
[WebAssembly] Implement more WebAssembly binary encoding. This changes locals from being declared by the emitLocal hook in WebAssemblyTargetStreamer, rather than with an instruction. After exploring the infastructure in LLVM more, this seems to make more sense since declaring locals doesn't use an encoded opcode. This also adds more 0xd opcodes, type encodings, and miscellaneous binary encoding bits. llvm-svn: 285040
2016-10-25 07:27:49 +08:00
/// Instruction opcodes emitted via means other than CodeGen.
static const unsigned Nop = 0x01;
static const unsigned End = 0x0b;
[WebAssembly] Use LEB encoding for value types Previously we were using the encoded LEB hex values for the value types. This change uses the decoded negative value and the LEB encoder to write them out. Differential Revision: https://reviews.llvm.org/D30847 Patch by Sam Clegg llvm-svn: 297777
2017-03-15 04:23:22 +08:00
wasm::ValType toValType(const MVT &Ty);
[WebAssembly] Implement more WebAssembly binary encoding. This changes locals from being declared by the emitLocal hook in WebAssemblyTargetStreamer, rather than with an instruction. After exploring the infastructure in LLVM more, this seems to make more sense since declaring locals doesn't use an encoded opcode. This also adds more 0xd opcodes, type encodings, and miscellaneous binary encoding bits. llvm-svn: 285040
2016-10-25 07:27:49 +08:00
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
} // end namespace WebAssembly
} // end namespace llvm
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
#endif