2016-06-24 14:58:01 +08:00
|
|
|
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
|
|
|
|
; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}test_loop:
|
2018-05-18 00:45:01 +08:00
|
|
|
; GCN: s_and_b64 vcc, exec, -1
|
Codegen: Make chains from trellis-shaped CFGs
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:
A B
|\ /|
| \ / |
| X |
| / \ |
|/ \|
C D
would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.
because of this we can tail duplicate to extend existing trellises.
As an example consider the following CFG:
B D F H
/ \ / \ / \ / \
A---C---E---G---Ret
Where A,C,E,G are all small (Currently 2 instructions).
The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.
The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret
define void @straight_test(i32 %tag) {
entry:
br label %test1
test1: ; A
%tagbit1 = and i32 %tag, 1
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
call void @a()
br label %test2
test2: ; C
%tagbit2 = and i32 %tag, 2
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
call void @b()
br label %test3
test3: ; E
%tagbit3 = and i32 %tag, 4
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
call void @c()
br label %test4
test4: ; G
%tagbit4 = and i32 %tag, 8
%tagbit4eq0 = icmp eq i32 %tagbit4, 0
br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
call void @d()
br label %exit
exit:
ret void
}
here is the layout after D27742:
straight_test: # @straight_test
; ... Prologue elided
; BB#0: # %entry ; A (merged with test1)
; ... More prologue elided
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_2
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_3
b .LBB0_4
.LBB0_2: # %optional1 ; B (copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_4
.LBB0_3: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_5
b .LBB0_6
.LBB0_4: # %optional2 ; D (copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_5: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
b .LBB0_7
.LBB0_6: # %optional3 ; F (copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit ; Ret
ld 30, 96(1) # 8-byte Folded Reload
addi 1, 1, 112
ld 0, 16(1)
mtlr 0
blr
The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.
This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.
Here is the resulting concrete layout:
straight_test: # @straight_test
; BB#0: # %entry ; A (merged with test1)
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_4
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_5
.LBB0_2: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_3: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
bne 0, .LBB0_7
b .LBB0_8
.LBB0_4: # %optional1 ; B (Copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_2
.LBB0_5: # %optional2 ; D (Copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_3
.LBB0_6: # %optional3 ; F (Copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit
Differential Revision: https://reviews.llvm.org/D28522
llvm-svn: 295223
2017-02-16 03:49:14 +08:00
|
|
|
; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: ; %for.body{{$}}
|
2016-06-24 14:58:01 +08:00
|
|
|
; GCN: ds_read_b32
|
|
|
|
|
; GCN: ds_write_b32
|
2018-05-18 00:45:01 +08:00
|
|
|
; GCN: s_cbranch_vccnz [[LABEL]]
|
2016-06-24 14:58:01 +08:00
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind {
|
2016-06-24 14:58:01 +08:00
|
|
|
entry:
|
|
|
|
|
%cmp = icmp eq i32 %n, -1
|
|
|
|
|
br i1 %cmp, label %for.exit, label %for.body
|
|
|
|
|
|
|
|
|
|
for.exit:
|
|
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
for.body:
|
|
|
|
|
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
|
|
|
|
%tmp = add i32 %indvar, 32
|
|
|
|
|
%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
|
|
|
|
|
%vecload = load float, float addrspace(3)* %arrayidx, align 4
|
|
|
|
|
%add = fadd float %vecload, 1.0
|
|
|
|
|
store float %add, float addrspace(3)* %arrayidx, align 8
|
|
|
|
|
%inc = add i32 %indvar, 1
|
|
|
|
|
br label %for.body
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: @loop_const_true
|
|
|
|
|
; GCN: [[LABEL:BB[0-9+]_[0-9]+]]:
|
|
|
|
|
; GCN: ds_read_b32
|
|
|
|
|
; GCN: ds_write_b32
|
|
|
|
|
; GCN: s_branch [[LABEL]]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind {
|
2016-06-24 14:58:01 +08:00
|
|
|
entry:
|
|
|
|
|
br label %for.body
|
|
|
|
|
|
|
|
|
|
for.exit:
|
|
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
for.body:
|
|
|
|
|
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
|
|
|
|
%tmp = add i32 %indvar, 32
|
|
|
|
|
%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
|
|
|
|
|
%vecload = load float, float addrspace(3)* %arrayidx, align 4
|
|
|
|
|
%add = fadd float %vecload, 1.0
|
|
|
|
|
store float %add, float addrspace(3)* %arrayidx, align 8
|
|
|
|
|
%inc = add i32 %indvar, 1
|
|
|
|
|
br i1 true, label %for.body, label %for.exit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}loop_const_false:
|
|
|
|
|
; GCN-NOT: s_branch
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @loop_const_false(float addrspace(3)* %ptr, i32 %n) nounwind {
|
2016-06-24 14:58:01 +08:00
|
|
|
entry:
|
|
|
|
|
br label %for.body
|
|
|
|
|
|
|
|
|
|
for.exit:
|
|
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
; XXX - Should there be an S_ENDPGM?
|
|
|
|
|
for.body:
|
|
|
|
|
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
|
|
|
|
%tmp = add i32 %indvar, 32
|
|
|
|
|
%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
|
|
|
|
|
%vecload = load float, float addrspace(3)* %arrayidx, align 4
|
|
|
|
|
%add = fadd float %vecload, 1.0
|
|
|
|
|
store float %add, float addrspace(3)* %arrayidx, align 8
|
|
|
|
|
%inc = add i32 %indvar, 1
|
|
|
|
|
br i1 false, label %for.body, label %for.exit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}loop_const_undef:
|
|
|
|
|
; GCN-NOT: s_branch
|
|
|
|
|
; GCN: s_endpgm
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @loop_const_undef(float addrspace(3)* %ptr, i32 %n) nounwind {
|
2016-06-24 14:58:01 +08:00
|
|
|
entry:
|
|
|
|
|
br label %for.body
|
|
|
|
|
|
|
|
|
|
for.exit:
|
|
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
; XXX - Should there be an s_endpgm?
|
|
|
|
|
for.body:
|
|
|
|
|
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
|
|
|
|
%tmp = add i32 %indvar, 32
|
|
|
|
|
%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
|
|
|
|
|
%vecload = load float, float addrspace(3)* %arrayidx, align 4
|
|
|
|
|
%add = fadd float %vecload, 1.0
|
|
|
|
|
store float %add, float addrspace(3)* %arrayidx, align 8
|
|
|
|
|
%inc = add i32 %indvar, 1
|
|
|
|
|
br i1 undef, label %for.body, label %for.exit
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}loop_arg_0:
|
|
|
|
|
; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
|
[AMDGPU] Fixed incorrect uniform branch condition
Summary:
I had a case where multiple nested uniform ifs resulted in code that did
v_cmp comparisons, combining the results with s_and_b64, s_or_b64 and
s_xor_b64 and using the resulting mask in s_cbranch_vccnz, without first
ensuring that bits for inactive lanes were clear.
There was already code for inserting an "s_and_b64 vcc, exec, vcc" to
clear bits for inactive lanes in the case that the branch is instruction
selected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz in
SIFixSGPRCopies. I have added the same code into SILowerControlFlow for
the case that the branch is instruction selected as s_cbranch_vccnz.
This de-optimizes the code in some cases where the s_and is not needed,
because vcc is the result of a v_cmp, or multiple v_cmp instructions
combined by s_and/s_or. We should add a pass to re-optimize those cases.
Reviewers: arsenm, kzhuravl
Subscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnle
Differential Revision: https://reviews.llvm.org/D41292
llvm-svn: 322119
2018-01-10 05:34:43 +08:00
|
|
|
; GCN: v_cmp_eq_u32{{[^,]*}}, 1,
|
2016-06-24 14:58:01 +08:00
|
|
|
|
|
|
|
|
; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]
|
2016-11-29 08:46:46 +08:00
|
|
|
; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80
|
|
|
|
|
; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 4
|
|
|
|
|
|
2016-06-24 14:58:01 +08:00
|
|
|
; GCN: s_cbranch_vccnz [[LOOPBB]]
|
2017-12-05 01:18:51 +08:00
|
|
|
; GCN-NEXT: ; %bb.2
|
2016-06-24 14:58:01 +08:00
|
|
|
; GCN-NEXT: s_endpgm
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
define amdgpu_kernel void @loop_arg_0(float addrspace(3)* %ptr, i32 %n) nounwind {
|
2016-06-24 14:58:01 +08:00
|
|
|
entry:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 17:54:49 +08:00
|
|
|
%cond = load volatile i1, i1 addrspace(3)* null
|
2016-06-24 14:58:01 +08:00
|
|
|
br label %for.body
|
|
|
|
|
|
|
|
|
|
for.exit:
|
|
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
for.body:
|
|
|
|
|
%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
|
|
|
|
|
%tmp = add i32 %indvar, 32
|
|
|
|
|
%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
|
|
|
|
|
%vecload = load float, float addrspace(3)* %arrayidx, align 4
|
|
|
|
|
%add = fadd float %vecload, 1.0
|
|
|
|
|
store float %add, float addrspace(3)* %arrayidx, align 8
|
|
|
|
|
%inc = add i32 %indvar, 1
|
|
|
|
|
br i1 %cond, label %for.body, label %for.exit
|
|
|
|
|
}
|