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llvm-project/llvm/lib/Target/ARM/CMakeLists.txt

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CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
set(LLVM_TARGET_DEFINITIONS ARM.td)
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just added a layer of indirection with no value (not even conciseness). llvm-svn: 143727
2011-11-05 03:04:23 +08:00
tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM ARMGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
Clean up a pile of hacks in our CMake build relating to TableGen. The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
2011-07-26 08:09:08 +08:00
add_public_tablegen_target(ARMCommonTableGen)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
CMake: Turned some libraries into partially linked objects. Corrected names of LLVMCore and ARMCodeGen. llvm-svn: 57943
2008-10-22 10:51:53 +08:00
add_llvm_target(ARMCodeGen
Update CMake files. llvm-svn: 108787
2010-07-20 08:08:13 +08:00
ARMAsmPrinter.cpp
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
2009-07-09 00:09:28 +08:00
ARMBaseInstrInfo.cpp
Fix cmake build. Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt llvm-svn: 75035
2009-07-09 04:13:41 +08:00
ARMBaseRegisterInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMCodeEmitter.cpp
ARMConstantIslandPass.cpp
ARMConstantPoolValue.cpp
Odd additional stub framework for the ARM MC ELF emission. llc now recognizes the "intent" to support MC/obj emission for ARM, but given that they are all stubs, it asserts on --filetype=obj --march=arm Patch by Jason Kim. llvm-svn: 114856
2010-09-28 02:31:37 +08:00
ARMELFWriterInfo.cpp
Update CMake file. llvm-svn: 86325
2009-11-07 11:26:59 +08:00
ARMExpandPseudoInsts.cpp
Update CMake files. llvm-svn: 109081
2010-07-22 14:00:01 +08:00
ARMFastISel.cpp
Update CMake stuff llvm-svn: 123171
2011-01-10 20:39:23 +08:00
ARMFrameLowering.cpp
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
2010-12-06 06:04:16 +08:00
ARMHazardRecognizer.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMISelDAGToDAG.cpp
ARMISelLowering.cpp
Update CMake file. llvm-svn: 85861
2009-11-03 12:14:12 +08:00
ARMInstrInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMJITInfo.cpp
ARMLoadStoreOptimizer.cpp
Update CMake files. llvm-svn: 108787
2010-07-20 08:08:13 +08:00
ARMMCInstLower.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMRegisterInfo.cpp
Update CMake files. llvm-svn: 108787
2010-07-20 08:08:13 +08:00
ARMSelectionDAGInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMSubtarget.cpp
ARMTargetMachine.cpp
The ARM EH experiment worked! Place the LSDA into the TEXT section for ARM platforms. This involves making the encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The references to the type infos are then non-lazy pointers. Revision 98019 changed the encoding of non-lazy pointers to add the symbol to the non-lazy pointer definition if it's a local symbol (otherwise, it's external and set to '0' so that the loader can adjust it to the real value). This paved the way for this change to work on ARM. llvm-svn: 98068
2010-03-10 02:31:07 +08:00
ARMTargetObjectFile.cpp
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. llvm-svn: 120966
2010-12-06 07:08:57 +08:00
MLxExpansionPass.cpp
Update CMake stuff llvm-svn: 123171
2011-01-10 20:39:23 +08:00
Thumb1FrameLowering.cpp
Unbreak CMake build. llvm-svn: 140655
2011-09-28 07:29:59 +08:00
Thumb1InstrInfo.cpp
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
2009-07-03 06:18:33 +08:00
Thumb1RegisterInfo.cpp
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing the cmake build. llvm-svn: 75246
2009-07-10 16:31:50 +08:00
Thumb2ITBlockPass.cpp
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
2009-07-03 06:18:33 +08:00
Thumb2InstrInfo.cpp
Thumb2RegisterInfo.cpp
Update CMake llvm-svn: 78475
2009-08-09 01:03:13 +08:00
Thumb2SizeReduction.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
)
CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. llvm-svn: 122623
2010-12-29 11:59:27 +08:00
lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. llvm-svn: 144794
2011-11-16 17:18:28 +08:00
# workaround for hanging compilation on MSVC9, 10
if( MSVC_VERSION EQUAL 1600 OR MSVC_VERSION EQUAL 1500 )
CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. llvm-svn: 122623
2010-12-29 11:59:27 +08:00
set_property(
SOURCE ARMISelLowering.cpp
PROPERTY COMPILE_FLAGS "/Od"
)
endif()
Use explicit add_subdirectory's for LLVM target sublibraries instead of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
2011-02-20 10:55:27 +08:00
add_subdirectory(TargetInfo)
add_subdirectory(AsmParser)
add_subdirectory(Disassembler)
add_subdirectory(InstPrinter)
Add ARM MC registry routines. llvm-svn: 134547
2011-07-07 06:02:34 +08:00
add_subdirectory(MCTargetDesc)