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llvm-project/llvm/test/CodeGen/X86/combine-udiv.ll

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[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Add common CHECK prefix for tests without SSE/AVX codegen llvm-svn: 321810
2018-01-05 02:23:46 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
[X86] Add srem/udiv/urem by one combine tests llvm-svn: 321826
2018-01-05 06:08:36 +08:00
; fold (udiv x, 1) -> x
define i32 @combine_udiv_by_one(i32 %x) {
; CHECK-LABEL: combine_udiv_by_one:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%1 = udiv i32 %x, 1
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_by_one(<4 x i32> %x) {
; CHECK-LABEL: combine_vec_udiv_by_one:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = udiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %1
}
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; fold (udiv x, -1) -> select((icmp eq x, -1), 1, 0)
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
define i32 @combine_udiv_by_negone(i32 %x) {
; CHECK-LABEL: combine_udiv_by_negone:
; CHECK: # %bb.0:
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpl $-1, %edi
; CHECK-NEXT: sete %al
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
; CHECK-NEXT: retq
%1 = udiv i32 %x, -1
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_by_negone(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_negone:
; SSE: # %bb.0:
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
; SSE-NEXT: psrld $31, %xmm0
; SSE-NEXT: retq
;
[DAGCombiner] Add special case fast paths for udiv x,1 and udiv x,-1 udiv x,-1 was going down the (slow) BuildUDIV route resulting in unnecessary shifts. llvm-svn: 336701
2018-07-11 00:33:07 +08:00
; AVX-LABEL: combine_vec_udiv_by_negone:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX-NEXT: retq
[X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694
2018-07-11 00:08:28 +08:00
%1 = udiv <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %1
}
; fold (udiv x, INT_MIN) -> (srl x, 31)
define i32 @combine_udiv_by_minsigned(i32 %x) {
; CHECK-LABEL: combine_udiv_by_minsigned:
; CHECK: # %bb.0:
; CHECK-NEXT: shrl $31, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%1 = udiv i32 %x, -2147483648
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_by_minsigned(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_minsigned:
; SSE: # %bb.0:
; SSE-NEXT: psrld $31, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_by_minsigned:
; AVX: # %bb.0:
; AVX-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = udiv <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
ret <4 x i32> %1
}
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM llvm-svn: 321807
2018-01-05 02:20:46 +08:00
; TODO fold (udiv x, x) -> 1
define i32 @combine_udiv_dupe(i32 %x) {
[X86] Add common CHECK prefix for tests without SSE/AVX codegen llvm-svn: 321810
2018-01-05 02:23:46 +08:00
; CHECK-LABEL: combine_udiv_dupe:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: divl %edi
; CHECK-NEXT: retq
[X86] Show missed combine for X/X for SDIV/UDIV and X%X for SREM/UREM llvm-svn: 321807
2018-01-05 02:20:46 +08:00
%1 = udiv i32 %x, %x
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_dupe(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_dupe:
; SSE: # %bb.0:
; SSE-NEXT: pextrd $1, %xmm0, %eax
; SSE-NEXT: xorl %edx, %edx
; SSE-NEXT: divl %eax
; SSE-NEXT: movl %eax, %ecx
; SSE-NEXT: movd %xmm0, %eax
; SSE-NEXT: xorl %edx, %edx
; SSE-NEXT: divl %eax
; SSE-NEXT: movd %eax, %xmm1
; SSE-NEXT: pinsrd $1, %ecx, %xmm1
; SSE-NEXT: pextrd $2, %xmm0, %eax
; SSE-NEXT: xorl %edx, %edx
; SSE-NEXT: divl %eax
; SSE-NEXT: pinsrd $2, %eax, %xmm1
; SSE-NEXT: pextrd $3, %xmm0, %eax
; SSE-NEXT: xorl %edx, %edx
; SSE-NEXT: divl %eax
; SSE-NEXT: pinsrd $3, %eax, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_dupe:
; AVX: # %bb.0:
; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: xorl %edx, %edx
; AVX-NEXT: divl %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: xorl %edx, %edx
; AVX-NEXT: divl %eax
; AVX-NEXT: vmovd %eax, %xmm1
; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: xorl %edx, %edx
; AVX-NEXT: divl %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: xorl %edx, %edx
; AVX-NEXT: divl %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
; AVX-NEXT: retq
%1 = udiv <4 x i32> %x, %x
ret <4 x i32> %1
}
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; fold (udiv x, (1 << c)) -> x >>u c
define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: # %bb.0:
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: psrld $2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_by_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX: # %bb.0:
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = udiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_udiv_by_pow2b(<4 x i32> %x) {
; SSE-LABEL: combine_vec_udiv_by_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrld $3, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE-NEXT: psrld $4, %xmm0
; SSE-NEXT: psrld $2, %xmm2
; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; SSE-NEXT: movdqa %xmm1, %xmm0
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: retq
;
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX1-LABEL: combine_vec_udiv_by_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX1-NEXT: vpsrld $4, %xmm0, %xmm1
; AVX1-NEXT: vpsrld $2, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vpsrld $3, %xmm0, %xmm2
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = udiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
ret <4 x i32> %1
}
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
define <4 x i32> @combine_vec_udiv_by_pow2c(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_udiv_by_pow2c:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: # %bb.0:
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441) As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
2018-05-17 04:52:52 +08:00
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrld %xmm2, %xmm3
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441) As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
2018-05-17 04:52:52 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: psrld %xmm4, %xmm5
; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrld %xmm1, %xmm3
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
; SSE-NEXT: psrld %xmm1, %xmm0
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
; SSE-NEXT: retq
;
; AVX1-LABEL: combine_vec_udiv_by_pow2c:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_pow2c:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[SelectionDAG] Recognise splat vector isKnownToBeAPowerOfTwo one/sign bit shift cases. llvm-svn: 301303
2017-04-25 20:29:07 +08:00
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
%1 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
%2 = udiv <4 x i32> %x, %1
ret <4 x i32> %2
}
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
define <4 x i32> @combine_vec_udiv_by_shl_pow2a(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_udiv_by_shl_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: # %bb.0:
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441) As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
2018-05-17 04:52:52 +08:00
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
[DAGCombiner] Add splatted vector support to (udiv x, (shl pow2, y)) -> x >>u (log2(pow2)+y) llvm-svn: 284491
2016-10-19 00:36:00 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrld %xmm2, %xmm3
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441) As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
2018-05-17 04:52:52 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: psrld %xmm4, %xmm5
; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrld %xmm1, %xmm3
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
; SSE-NEXT: psrld %xmm1, %xmm0
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: retq
;
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-LABEL: combine_vec_udiv_by_shl_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_shl_pow2a:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[X86][AVX] Regenerate combine tests with constant broadcast comments llvm-svn: 308128
2017-07-16 19:36:11 +08:00
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2,2,2,2]
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = shl <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %y
%2 = udiv <4 x i32> %x, %1
ret <4 x i32> %2
}
define <4 x i32> @combine_vec_udiv_by_shl_pow2b(<4 x i32> %x, <4 x i32> %y) {
; SSE-LABEL: combine_vec_udiv_by_shl_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE: # %bb.0:
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: paddd {{.*}}(%rip), %xmm1
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441) As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
2018-05-17 04:52:52 +08:00
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrld %xmm2, %xmm3
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441) As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure. Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs. Differential Revision: https://reviews.llvm.org/D46959 llvm-svn: 332524
2018-05-17 04:52:52 +08:00
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: psrld %xmm4, %xmm5
; SSE-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: psrld %xmm1, %xmm3
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
; SSE-NEXT: psrld %xmm1, %xmm0
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
; SSE-NEXT: retq
;
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-LABEL: combine_vec_udiv_by_shl_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX1: # %bb.0:
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_udiv_by_shl_pow2b:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX2: # %bb.0:
[DAGCombiner] Try to use SelectionDAG::isKnownToBeAPowerOfTwo instead of just APInt::isPowerOf2 Generalize sdiv/udiv/srem/urem combines using APInt::isPowerOf2, which only works for const/splat-const values, to call SelectionDAG::isKnownToBeAPowerOfTwo instead which recognises many more cases. Added a DAGCombiner::BuildLogBase2 helper since PowerOf2 combines often involve taking the log2 of such a value. Differential Revision: https://reviews.llvm.org/D27714 llvm-svn: 289654
2016-12-14 23:08:13 +08:00
; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
[X86][SSE] Add AVX1 tests to sdiv/udiv srem/urem combine tests As requested on D27714 llvm-svn: 289652
2016-12-14 22:39:51 +08:00
; AVX2-NEXT: retq
[X86][SSE] Added vector udiv combine tests llvm-svn: 281842
2016-09-18 06:02:23 +08:00
%1 = shl <4 x i32> <i32 1, i32 4, i32 8, i32 16>, %y
%2 = udiv <4 x i32> %x, %1
ret <4 x i32> %2
}
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
; fold (udiv x, c1)
define i32 @combine_udiv_uniform(i32 %x) {
; CHECK-LABEL: combine_udiv_uniform:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %ecx
; CHECK-NEXT: movl $2987803337, %eax # imm = 0xB21642C9
; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: shrq $36, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
%1 = udiv i32 %x, 23
ret i32 %1
}
define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
; SSE-LABEL: combine_vec_udiv_uniform:
; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [25645,25645,25645,25645,25645,25645,25645,25645]
; SSE-NEXT: pmulhuw %xmm0, %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: psrlw $1, %xmm0
; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: psrlw $4, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_uniform:
; AVX: # %bb.0:
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 23, i16 23, i16 23, i16 23, i16 23, i16 23, i16 23, i16 23>
ret <8 x i16> %1
}
define <8 x i16> @combine_vec_udiv_nonuniform(<8 x i16> %x) {
; SSE-LABEL: combine_vec_udiv_nonuniform:
; SSE: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrlw $3, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: movl $32768, %eax # imm = 0x8000
; SSE-NEXT: movd %eax, %xmm2
; SSE-NEXT: pmulhuw %xmm0, %xmm2
; SSE-NEXT: paddw %xmm1, %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm0 = <4096,2048,8,u,u,2,2,u>
; SSE-NEXT: pmulhuw %xmm2, %xmm0
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3,4],xmm0[5,6],xmm2[7]
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_nonuniform:
; AVX: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; AVX-NEXT: vpsrlw $3, %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7]
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: movl $32768, %eax # imm = 0x8000
; AVX-NEXT: vmovd %eax, %xmm2
; AVX-NEXT: vpmulhuw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4],xmm1[5,6],xmm0[7]
[X86] Add UDIV by uniform/non-uniform constant tests llvm-svn: 336894
2018-07-12 17:04:28 +08:00
; AVX-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 23, i16 34, i16 -23, i16 56, i16 128, i16 -1, i16 -256, i16 -32768>
ret <8 x i16> %1
}
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
; SSE-LABEL: combine_vec_udiv_nonuniform2:
; SSE: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrlw $1, %xmm1
; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3,4,5,6,7]
; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm1
; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm1
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_nonuniform2:
; AVX: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7]
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; AVX-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 -34, i16 35, i16 36, i16 -37, i16 38, i16 -39, i16 40, i16 -41>
ret <8 x i16> %1
}
define <8 x i16> @combine_vec_udiv_nonuniform3(<8 x i16> %x) {
; SSE-LABEL: combine_vec_udiv_nonuniform3:
; SSE: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9363,25645,18351,12137,2115,23705,1041,517]
; SSE-NEXT: pmulhuw %xmm0, %xmm1
; SSE-NEXT: psubw %xmm1, %xmm0
; SSE-NEXT: psrlw $1, %xmm0
; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm0
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_nonuniform3:
; AVX: # %bb.0:
[TargetLowering] Add support for non-uniform vectors to BuildUDIV This patch refactors the existing TargetLowering::BuildUDIV base implementation to support non-uniform constant vector denominators. It also includes a fold for MULHU by pow2 constants to SRL which can now more readily occur from BuildUDIV. Differential Revision: https://reviews.llvm.org/D49248 llvm-svn: 339121
2018-08-07 17:51:34 +08:00
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
[X86][SSE] Add more UDIV nonuniform-constant vector tests Ensure we cover all paths for vector data as requested on D49248 llvm-svn: 338698
2018-08-02 18:53:53 +08:00
; AVX-NEXT: retq
%1 = udiv <8 x i16> %x, <i16 7, i16 23, i16 25, i16 27, i16 31, i16 47, i16 63, i16 127>
ret <8 x i16> %1
}
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
; TODO: Handle udiv-by-one
define <8 x i16> @pr38477(<8 x i16> %a0) {
; SSE-LABEL: pr38477:
; SSE: # %bb.0:
[X86][SSE] PR38477 test is more cleanly tested with udiv instead of urem Making the test use urem relies on it calling udiv-like combines, but the real issue is with the udiv so we're better off using that directly. llvm-svn: 339247
2018-08-08 22:11:44 +08:00
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
; SSE-NEXT: pextrw $1, %xmm1, %eax
; SSE-NEXT: imull $4957, %eax, %ecx # imm = 0x135D
; SSE-NEXT: shrl $16, %ecx
; SSE-NEXT: subl %ecx, %eax
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
; SSE-NEXT: movzwl %ax, %eax
; SSE-NEXT: shrl %eax
; SSE-NEXT: addl %ecx, %eax
[X86][SSE] PR38477 test is more cleanly tested with udiv instead of urem Making the test use urem relies on it calling udiv-like combines, but the real issue is with the udiv so we're better off using that directly. llvm-svn: 339247
2018-08-08 22:11:44 +08:00
; SSE-NEXT: shrl $6, %eax
; SSE-NEXT: pinsrw $1, %eax, %xmm0
; SSE-NEXT: pextrw $2, %xmm1, %eax
; SSE-NEXT: imull $57457, %eax, %eax # imm = 0xE071
; SSE-NEXT: shrl $22, %eax
; SSE-NEXT: pinsrw $2, %eax, %xmm0
; SSE-NEXT: pextrw $3, %xmm1, %eax
; SSE-NEXT: imull $4103, %eax, %eax # imm = 0x1007
; SSE-NEXT: shrl $28, %eax
; SSE-NEXT: pinsrw $3, %eax, %xmm0
; SSE-NEXT: pextrw $4, %xmm1, %eax
; SSE-NEXT: movl %eax, %ecx
; SSE-NEXT: shll $14, %ecx
; SSE-NEXT: addl %eax, %ecx
; SSE-NEXT: shrl $30, %ecx
; SSE-NEXT: pinsrw $4, %ecx, %xmm0
; SSE-NEXT: pextrw $5, %xmm1, %eax
; SSE-NEXT: imull $35545, %eax, %eax # imm = 0x8AD9
; SSE-NEXT: shrl $22, %eax
; SSE-NEXT: pinsrw $5, %eax, %xmm0
; SSE-NEXT: pextrw $6, %xmm1, %eax
; SSE-NEXT: shrl $5, %eax
; SSE-NEXT: pinsrw $6, %eax, %xmm0
; SSE-NEXT: pextrw $7, %xmm1, %eax
; SSE-NEXT: imull $2115, %eax, %ecx # imm = 0x843
; SSE-NEXT: shrl $16, %ecx
; SSE-NEXT: subl %ecx, %eax
; SSE-NEXT: movzwl %ax, %eax
; SSE-NEXT: shrl %eax
; SSE-NEXT: addl %ecx, %eax
; SSE-NEXT: shrl $4, %eax
; SSE-NEXT: pinsrw $7, %eax, %xmm0
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: pr38477:
; AVX: # %bb.0:
[X86][SSE] PR38477 test is more cleanly tested with udiv instead of urem Making the test use urem relies on it calling udiv-like combines, but the real issue is with the udiv so we're better off using that directly. llvm-svn: 339247
2018-08-08 22:11:44 +08:00
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
; AVX-NEXT: vpextrw $1, %xmm0, %eax
; AVX-NEXT: imull $4957, %eax, %ecx # imm = 0x135D
; AVX-NEXT: shrl $16, %ecx
; AVX-NEXT: subl %ecx, %eax
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
; AVX-NEXT: movzwl %ax, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
[X86][SSE] PR38477 test is more cleanly tested with udiv instead of urem Making the test use urem relies on it calling udiv-like combines, but the real issue is with the udiv so we're better off using that directly. llvm-svn: 339247
2018-08-08 22:11:44 +08:00
; AVX-NEXT: shrl $6, %eax
; AVX-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrw $2, %xmm0, %eax
; AVX-NEXT: imull $57457, %eax, %eax # imm = 0xE071
; AVX-NEXT: shrl $22, %eax
; AVX-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrw $3, %xmm0, %eax
; AVX-NEXT: imull $4103, %eax, %eax # imm = 0x1007
; AVX-NEXT: shrl $28, %eax
; AVX-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrw $4, %xmm0, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shll $14, %ecx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: shrl $30, %ecx
; AVX-NEXT: vpinsrw $4, %ecx, %xmm1, %xmm1
; AVX-NEXT: vpextrw $5, %xmm0, %eax
; AVX-NEXT: imull $35545, %eax, %eax # imm = 0x8AD9
; AVX-NEXT: shrl $22, %eax
; AVX-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrw $6, %xmm0, %eax
; AVX-NEXT: shrl $5, %eax
; AVX-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
; AVX-NEXT: vpextrw $7, %xmm0, %eax
; AVX-NEXT: imull $2115, %eax, %ecx # imm = 0x843
; AVX-NEXT: shrl $16, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: movzwl %ax, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $4, %eax
; AVX-NEXT: vpinsrw $7, %eax, %xmm1, %xmm0
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
; AVX-NEXT: retq
[X86][SSE] PR38477 test is more cleanly tested with udiv instead of urem Making the test use urem relies on it calling udiv-like combines, but the real issue is with the udiv so we're better off using that directly. llvm-svn: 339247
2018-08-08 22:11:44 +08:00
%rem = udiv <8 x i16> %a0, <i16 1, i16 119, i16 73, i16 -111, i16 -3, i16 118, i16 32, i16 31>
[TargetLowering] BuildUDIV - Early out for divide by one (PR38477) We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
2018-08-08 18:00:54 +08:00
ret <8 x i16> %rem
}