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llvm-project/llvm/test/CodeGen/X86/extract-bits.ll

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[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR Summary: This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction. The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop. For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case. Reviewers: RKSimon, spatel, lebedev.ri, andreadb Reviewed By: RKSimon Subscribers: llvm-commits, andreadb, RKSimon Differential Revision: https://reviews.llvm.org/D52570 llvm-svn: 343399
2018-09-30 11:01:46 +08:00
; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=-bmi,-tbm,-bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X86,NOBMI,X86-NOBMI
; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=+bmi,-tbm,-bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1NOTBM,X86-BMI1NOTBM
; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=+bmi,+tbm,-bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1TBM,X86-BMI1TBM
; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=+bmi,+tbm,+bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1BMI2,X86-BMI1BMI2,BMI1TBM,X86-BMI1TBM,BMI1TBMBMI2,X86-BMI1TBMBMI2
; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=+bmi,-tbm,+bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1BMI2,X86-BMI1BMI2,BMI1NOTBMBMI2,X86-BMI1NOTBMBMI2
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=-bmi,-tbm,-bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X64,NOBMI,X64-NOBMI
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+bmi,-tbm,-bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI1,X64-BMI1,BMI1NOTBM,X64-BMI1NOTBM
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+bmi,+tbm,-bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI1,X64-BMI1,BMI1TBM,X64-BMI1TBM
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+bmi,+tbm,+bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI1,X64-BMI1,BMI1BMI2,X64-BMI1BMI2,BMI1TBM,X64-BMI1TBM,BMI1TBMBMI2,X64-BMI1TBMBMI2
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+bmi,-tbm,+bmi2,+fast-bextr < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI1,X64-BMI1,BMI1BMI2,X64-BMI1BMI2,BMI1NOTBMBMI2,X64-BMI1NOTBMBMI2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; *Please* keep in sync with test/CodeGen/AArch64/extract-bits.ll
; https://bugs.llvm.org/show_bug.cgi?id=36419
; https://bugs.llvm.org/show_bug.cgi?id=37603
; https://bugs.llvm.org/show_bug.cgi?id=37610
; Patterns:
; a) (x >> start) & (1 << nbits) - 1
; b) (x >> start) & ~(-1 << nbits)
; c) (x >> start) & (-1 >> (32 - y))
; d) (x >> start) << (32 - y) >> (32 - y)
; are equivalent.
declare void @use32(i32)
declare void @use64(i64)
; ---------------------------------------------------------------------------- ;
; Pattern a. 32-bit
; ---------------------------------------------------------------------------- ;
define i32 @bextr32_a0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a0:
; X86-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: shll $8, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a0:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
define i32 @bextr32_a0_arithmetic(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a0_arithmetic:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: sarl %cl, %esi
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a0_arithmetic:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: sarl %cl, %edx
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a0_arithmetic:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: sarxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a0_arithmetic:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: sarl %cl, %edi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a0_arithmetic:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-BMI1NOTBM-NEXT: sarl %cl, %edi
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: bextrl %edx, %edi, %eax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a0_arithmetic:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: sarxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = ashr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
define i32 @bextr32_a1_indexzext(i32 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a1_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: shll $8, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a1_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a1_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a1_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_a2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a2_load:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a2_load:
; X86-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%eax), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a2_load:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: shrxl %edx, (%ecx), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a2_load:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl (%rdi), %esi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %esi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %esi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a2_load:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, (%rdi), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a2_load:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_a3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a3_load_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%eax), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: shrxl %edx, (%ecx), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a3_load_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl (%rdi), %esi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %esi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %esi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, (%rdi), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_a4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a4_commutative:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a4_commutative:
; X86-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: shll $8, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a4_commutative:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a4_commutative:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a4_commutative:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a4_commutative:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %shifted, %mask ; swapped order
ret i32 %masked
}
define i32 @bextr32_a5_skipextrauses(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_a5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: movl $1, %esi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: decl %esi
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %eax, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_a5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl %al, %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %eax, (%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X86-BMI1NOTBM-NEXT: addl $8, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_a5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %esi
; X86-BMI1BMI2-NEXT: movl %ecx, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: addl $8, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_a5_skipextrauses:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $1, %ebx
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %ebx
; X64-NOBMI-NEXT: decl %ebx
; X64-NOBMI-NEXT: andl %edi, %ebx
; X64-NOBMI-NEXT: movl %esi, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: movl %ebx, %eax
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_a5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbx
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern Summary: Trivial continuation of D52304. While this pattern is not canonical, we do select it in the BZHI case, so this should not be any different. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52348 llvm-svn: 344902
2018-10-22 21:54:17 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: movl %ebx, %eax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_a5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %ebx
; X64-BMI1BMI2-NEXT: movl %esi, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %shifted
call void @use32(i32 %numskipbits)
ret i32 %masked
}
; 64-bit
define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB7_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB7_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shldl %cl, %eax, %edx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB7_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB7_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: addl $-1, %eax
; X86-NOBMI-NEXT: adcl $-1, %edx
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB7_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB7_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $1, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: movb %ch, %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %eax, %edx
; X86-BMI1NOTBM-NEXT: shll %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB7_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB7_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: addl $-1, %eax
; X86-BMI1NOTBM-NEXT: adcl $-1, %edx
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: andl %edi, %edx
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB7_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB7_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: movl %ebx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB7_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB7_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: addl $-1, %eax
; X86-BMI1BMI2-NEXT: adcl $-1, %edx
; X86-BMI1BMI2-NEXT: andl %esi, %eax
; X86-BMI1BMI2-NEXT: andl %edi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a0:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a0_arithmetic:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: sarl %cl, %esi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %edi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: je .LBB8_2
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: sarl $31, %eax
; X86-NOBMI-NEXT: movl %esi, %edi
; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB8_2:
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shldl %cl, %eax, %edx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: testb $32, %ch
; X86-NOBMI-NEXT: je .LBB8_4
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
; X86-NOBMI-NEXT: .LBB8_4:
; X86-NOBMI-NEXT: addl $-1, %eax
; X86-NOBMI-NEXT: adcl $-1, %edx
; X86-NOBMI-NEXT: andl %edi, %eax
; X86-NOBMI-NEXT: andl %esi, %edx
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a0_arithmetic:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %esi
; X86-BMI1NOTBM-NEXT: sarl %cl, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: je .LBB8_2
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: sarl $31, %eax
; X86-BMI1NOTBM-NEXT: movl %esi, %edi
; X86-BMI1NOTBM-NEXT: movl %eax, %esi
; X86-BMI1NOTBM-NEXT: .LBB8_2:
; X86-BMI1NOTBM-NEXT: movl $1, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: movb %ch, %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %eax, %edx
; X86-BMI1NOTBM-NEXT: shll %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %ch
; X86-BMI1NOTBM-NEXT: je .LBB8_4
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
; X86-BMI1NOTBM-NEXT: .LBB8_4:
; X86-BMI1NOTBM-NEXT: addl $-1, %eax
; X86-BMI1NOTBM-NEXT: adcl $-1, %edx
; X86-BMI1NOTBM-NEXT: andl %edi, %eax
; X86-BMI1NOTBM-NEXT: andl %esi, %edx
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a0_arithmetic:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: sarxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: je .LBB8_2
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: sarl $31, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: movl %eax, %edi
; X86-BMI1BMI2-NEXT: .LBB8_2:
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: movl %ebx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
; X86-BMI1BMI2-NEXT: je .LBB8_4
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
; X86-BMI1BMI2-NEXT: .LBB8_4:
; X86-BMI1BMI2-NEXT: addl $-1, %eax
; X86-BMI1BMI2-NEXT: adcl $-1, %edx
; X86-BMI1BMI2-NEXT: andl %esi, %eax
; X86-BMI1BMI2-NEXT: andl %edi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a0_arithmetic:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: sarq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a0_arithmetic:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-BMI1NOTBM-NEXT: sarq %cl, %rdi
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rdx, %rdi, %rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a0_arithmetic:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: sarxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%shifted = ashr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
define i64 @bextr64_a1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a1_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB9_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB9_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shldl %cl, %eax, %edx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB9_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB9_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: addl $-1, %eax
; X86-NOBMI-NEXT: adcl $-1, %edx
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB9_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB9_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $1, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: movb %ch, %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %eax, %edx
; X86-BMI1NOTBM-NEXT: shll %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB9_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB9_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: addl $-1, %eax
; X86-BMI1NOTBM-NEXT: adcl $-1, %edx
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: andl %edi, %edx
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a1_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB9_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB9_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: movl %ebx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB9_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB9_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: addl $-1, %eax
; X86-BMI1BMI2-NEXT: adcl $-1, %edx
; X86-BMI1BMI2-NEXT: andl %esi, %eax
; X86-BMI1BMI2-NEXT: andl %edi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a1_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a1_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: # kill: def $edx killed $edx def $rdx
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_a2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a2_load:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB10_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB10_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shldl %cl, %eax, %edx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB10_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB10_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: addl $-1, %eax
; X86-NOBMI-NEXT: adcl $-1, %edx
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a2_load:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %esi
; X86-BMI1NOTBM-NEXT: movl 4(%eax), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB10_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB10_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $1, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: movb %ch, %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %eax, %edx
; X86-BMI1NOTBM-NEXT: shll %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB10_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB10_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: addl $-1, %eax
; X86-BMI1NOTBM-NEXT: adcl $-1, %edx
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: andl %edi, %edx
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a2_load:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl (%eax), %esi
; X86-BMI1BMI2-NEXT: movl 4(%eax), %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB10_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB10_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: movl %ebx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB10_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB10_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: addl $-1, %eax
; X86-BMI1BMI2-NEXT: adcl $-1, %edx
; X86-BMI1BMI2-NEXT: andl %esi, %eax
; X86-BMI1BMI2-NEXT: andl %edi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a2_load:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq (%rdi), %rsi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rsi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decq %rax
; X64-NOBMI-NEXT: andq %rsi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a2_load:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rdi), %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a2_load:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_a3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a3_load_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB11_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB11_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shldl %cl, %eax, %edx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB11_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB11_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: addl $-1, %eax
; X86-NOBMI-NEXT: adcl $-1, %edx
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %esi
; X86-BMI1NOTBM-NEXT: movl 4(%eax), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB11_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB11_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $1, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: movb %ch, %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %eax, %edx
; X86-BMI1NOTBM-NEXT: shll %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB11_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB11_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: addl $-1, %eax
; X86-BMI1NOTBM-NEXT: adcl $-1, %edx
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: andl %edi, %edx
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl (%eax), %esi
; X86-BMI1BMI2-NEXT: movl 4(%eax), %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB11_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB11_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: movl %ebx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB11_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB11_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: addl $-1, %eax
; X86-BMI1BMI2-NEXT: adcl $-1, %edx
; X86-BMI1BMI2-NEXT: andl %esi, %eax
; X86-BMI1BMI2-NEXT: andl %edi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a3_load_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movq (%rdi), %rsi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrq %cl, %rsi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decq %rax
; X64-NOBMI-NEXT: andq %rsi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rdi), %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: # kill: def $edx killed $edx def $rdx
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a4_commutative:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %edx
; X86-NOBMI-NEXT: shrl %cl, %edx
; X86-NOBMI-NEXT: shrdl %cl, %esi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB12_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB12_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $1, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shldl %cl, %esi, %edi
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB12_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB12_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: addl $-1, %esi
; X86-NOBMI-NEXT: adcl $-1, %edi
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a4_commutative:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %esi, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB12_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB12_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $1, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
; X86-BMI1NOTBM-NEXT: movb %ch, %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %esi, %edi
; X86-BMI1NOTBM-NEXT: shll %cl, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %ch
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB12_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB12_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: addl $-1, %esi
; X86-BMI1NOTBM-NEXT: adcl $-1, %edi
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: andl %edi, %edx
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a4_commutative:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB12_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB12_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $1, %edi
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %esi
; X86-BMI1BMI2-NEXT: shlxl %ebx, %edi, %ecx
; X86-BMI1BMI2-NEXT: testb $32, %bl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB12_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ecx, %esi
; X86-BMI1BMI2-NEXT: xorl %ecx, %ecx
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB12_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: addl $-1, %ecx
; X86-BMI1BMI2-NEXT: adcl $-1, %esi
; X86-BMI1BMI2-NEXT: andl %ecx, %eax
; X86-BMI1BMI2-NEXT: andl %esi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a4_commutative:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a4_commutative:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a4_commutative:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %shifted, %mask ; swapped order
ret i64 %masked
}
define i64 @bextr64_a5_skipextrauses(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_a5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: subl $12, %esp
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %esi, %ebp
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: shrl %cl, %ebp
; X86-NOBMI-NEXT: shrdl %cl, %esi, %ebx
; X86-NOBMI-NEXT: testb $32, %al
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB13_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %ebp, %ebx
; X86-NOBMI-NEXT: xorl %ebp, %ebp
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB13_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $1, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shldl %cl, %esi, %edi
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: testb $32, %dl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: je .LBB13_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-NOBMI-NEXT: .LBB13_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: addl $-1, %esi
; X86-NOBMI-NEXT: adcl $-1, %edi
; X86-NOBMI-NEXT: andl %ebx, %esi
; X86-NOBMI-NEXT: andl %ebp, %edi
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NOBMI-NEXT: pushl %eax
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_a5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: subl $12, %esp
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %esi, %ebp
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebp
; X86-BMI1NOTBM-NEXT: shrdl %cl, %esi, %ebx
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB13_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %ebp, %ebx
; X86-BMI1NOTBM-NEXT: xorl %ebp, %ebp
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB13_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $1, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
; X86-BMI1NOTBM-NEXT: movl %edx, %ecx
; X86-BMI1NOTBM-NEXT: shldl %cl, %esi, %edi
; X86-BMI1NOTBM-NEXT: shll %cl, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %dl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB13_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1NOTBM-NEXT: .LBB13_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: addl $-1, %esi
; X86-BMI1NOTBM-NEXT: adcl $-1, %edi
; X86-BMI1NOTBM-NEXT: andl %ebx, %esi
; X86-BMI1NOTBM-NEXT: andl %ebp, %edi
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl {{[0-9]+}}(%esp)
; X86-BMI1NOTBM-NEXT: pushl %eax
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_a5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: subl $12, %esp
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %ebx
; X86-BMI1BMI2-NEXT: shrxl %eax, %esi, %ebp
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB13_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %ebp, %ebx
; X86-BMI1BMI2-NEXT: xorl %ebp, %ebp
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB13_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $1, %edi
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
; X86-BMI1BMI2-NEXT: movl %edx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %esi
; X86-BMI1BMI2-NEXT: shlxl %edx, %edi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %dl
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: je .LBB13_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][x86][AArch64] extract-bits.ll: add test with 'ashr'. llvm-svn: 346121
2018-11-05 17:20:08 +08:00
; X86-BMI1BMI2-NEXT: .LBB13_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: addl $-1, %edi
; X86-BMI1BMI2-NEXT: adcl $-1, %esi
; X86-BMI1BMI2-NEXT: andl %ebx, %edi
; X86-BMI1BMI2-NEXT: andl %ebp, %esi
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl {{[0-9]+}}(%esp)
; X86-BMI1BMI2-NEXT: pushl %eax
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: movl %edi, %eax
; X86-BMI1BMI2-NEXT: movl %esi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_a5_skipextrauses:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %ebx
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rbx
; X64-NOBMI-NEXT: decq %rbx
; X64-NOBMI-NEXT: andq %rdi, %rbx
; X64-NOBMI-NEXT: movq %rsi, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_a5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbx
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movq %rsi, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_a5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rbx
; X64-BMI1BMI2-NEXT: movq %rsi, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: movq %rbx, %rax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
call void @use64(i64 %numskipbits)
ret i64 %masked
}
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; 64-bit, but with 32-bit output
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; Everything done in 64-bit, truncation happens last.
define i32 @bextr64_32_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_a0:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: pushl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %edi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB14_2
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB14_2:
; X86-NOBMI-NEXT: movl $1, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %edx, %ecx
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: xorl %eax, %eax
; X86-NOBMI-NEXT: testb $32, %dl
; X86-NOBMI-NEXT: jne .LBB14_4
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %edi, %eax
; X86-NOBMI-NEXT: .LBB14_4:
; X86-NOBMI-NEXT: decl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-LABEL: bextr64_32_a0:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: jne .LBB14_2
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %esi
; X86-BMI1NOTBM-NEXT: .LBB14_2:
; X86-BMI1NOTBM-NEXT: movl $1, %edi
; X86-BMI1NOTBM-NEXT: movl %edx, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %dl
; X86-BMI1NOTBM-NEXT: jne .LBB14_4
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %edi, %eax
; X86-BMI1NOTBM-NEXT: .LBB14_4:
; X86-BMI1NOTBM-NEXT: decl %eax
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-LABEL: bextr64_32_a0:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: je .LBB14_2
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edx
; X86-BMI1BMI2-NEXT: .LBB14_2:
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
; X86-BMI1BMI2-NEXT: jne .LBB14_4
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: .LBB14_4:
; X86-BMI1BMI2-NEXT: decl %eax
; X86-BMI1BMI2-NEXT: andl %edx, %eax
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-LABEL: bextr64_32_a0:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: andl %edi, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-LABEL: bextr64_32_a0:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness Summary: Finally tying up loose ends here. The problem is quite simple: If we have pattern `(x >> start) & (1 << nbits) - 1`, and then truncate the result, that truncation will be propagated upwards, into the `and`. And that isn't currently handled. I'm only fixing pattern `a` here, the same fix will be needed for patterns `b`/`c` too. I *think* this isn't missing any extra legality checks, since we only look past truncations. Similary, i don't think we can get any other truncation there other than i64->i32. Reviewers: craig.topper, RKSimon, spatel Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62786 llvm-svn: 364417
2019-06-26 20:19:11 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-LABEL: bextr64_32_a0:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
[X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness Summary: Finally tying up loose ends here. The problem is quite simple: If we have pattern `(x >> start) & (1 << nbits) - 1`, and then truncate the result, that truncation will be propagated upwards, into the `and`. And that isn't currently handled. I'm only fixing pattern `a` here, the same fix will be needed for patterns `b`/`c` too. I *think* this isn't missing any extra legality checks, since we only look past truncations. Similary, i don't think we can get any other truncation there other than i64->i32. Reviewers: craig.topper, RKSimon, spatel Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62786 llvm-svn: 364417
2019-06-26 20:19:11 +08:00
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %shifted
%res = trunc i64 %masked to i32
ret i32 %res
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
}
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
define i32 @bextr64_32_a1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_a1:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: pushl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %edi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB15_2
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB15_2:
; X86-NOBMI-NEXT: movl $1, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: decl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-LABEL: bextr64_32_a1:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: jne .LBB15_2
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
; X86-BMI1NOTBM-NEXT: .LBB15_2:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-LABEL: bextr64_32_a1:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: pushl %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: je .LBB15_2
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
; X86-BMI1BMI2-NEXT: .LBB15_2:
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-LABEL: bextr64_32_a1:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: decl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-LABEL: bextr64_32_a1:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-LABEL: bextr64_32_a1:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
%shifted = lshr i64 %val, %numskipbits
%truncshifted = trunc i64 %shifted to i32
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %truncshifted
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
ret i32 %masked
}
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; Shifting happens in 64-bit, then truncation (with extra use).
; Masking is 32-bit.
define i32 @bextr64_32_a1_trunc_extrause(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_a1_trunc_extrause:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl %edx, %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: shrdl %cl, %edx, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB16_2
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB16_2:
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: movl $1, %eax
; X86-NOBMI-NEXT: movl %ebx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_a1_trunc_extrause:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: pushl %eax
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: jne .LBB16_2
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %esi
; X86-BMI1NOTBM-NEXT: .LBB16_2:
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: shll $8, %ebx
; X86-BMI1NOTBM-NEXT: bextrl %ebx, %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $4, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_a1_trunc_extrause:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: pushl %eax
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: je .LBB16_2
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %esi
; X86-BMI1BMI2-NEXT: .LBB16_2:
; X86-BMI1BMI2-NEXT: movl %esi, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %eax
; X86-BMI1BMI2-NEXT: addl $4, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_a1_trunc_extrause:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
; X64-NOBMI-NEXT: movl %edx, %ebp
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq %rdi, %rbx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movl %ebx, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %ebp, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %ebx, %eax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %rbp
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_a1_trunc_extrause:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
; X64-BMI1NOTBM-NEXT: movl %edx, %ebp
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
; X64-BMI1NOTBM-NEXT: movq %rdi, %rbx
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movl %ebx, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: shll $8, %ebp
; X64-BMI1NOTBM-NEXT: bextrl %ebp, %ebx, %eax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %rbp
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_a1_trunc_extrause:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebp
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rbx
; X64-BMI1BMI2-NEXT: movl %ebx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebp, %ebx, %eax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %rbp
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%truncshifted = trunc i64 %shifted to i32
call void @use32(i32 %truncshifted)
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %truncshifted
ret i32 %masked
}
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
; Masking is 64-bit. Then truncation.
define i32 @bextr64_32_a2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_a2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: pushl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %edi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; X86-NOBMI-NEXT: jne .LBB17_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; X86-NOBMI-NEXT: .LBB17_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: movl $1, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: decl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-LABEL: bextr64_32_a2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB17_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; X86-BMI1NOTBM-NEXT: .LBB17_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-LABEL: bextr64_32_a2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: pushl %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; X86-BMI1BMI2-NEXT: je .LBB17_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-bits.ll: add test with truncation with extra-use. That extra-use *should* prevent D56052 from looking past the trunc. llvm-svn: 351182
2019-01-15 18:36:20 +08:00
; X86-BMI1BMI2-NEXT: .LBB17_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-LABEL: bextr64_32_a2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-LABEL: bextr64_32_a2:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_a2:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%zextmask = zext i32 %mask to i64
%masked = and i64 %zextmask, %shifted
%truncmasked = trunc i64 %masked to i32
ret i32 %truncmasked
}
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; Shifting happens in 64-bit. Mask is 32-bit, but calculated in 64-bit.
; Masking is 64-bit. Then truncation.
define i32 @bextr64_32_a3(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_a3:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: shrdl %cl, %edi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB18_2
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
; X86-NOBMI-NEXT: .LBB18_2:
; X86-NOBMI-NEXT: movl $1, %edi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: xorl %eax, %eax
; X86-NOBMI-NEXT: testb $32, %dl
; X86-NOBMI-NEXT: jne .LBB18_4
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %edi, %eax
; X86-NOBMI-NEXT: .LBB18_4:
; X86-NOBMI-NEXT: decl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_a3:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: jne .LBB18_2
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %esi
; X86-BMI1NOTBM-NEXT: .LBB18_2:
; X86-BMI1NOTBM-NEXT: movl $1, %edi
; X86-BMI1NOTBM-NEXT: movl %edx, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %dl
; X86-BMI1NOTBM-NEXT: jne .LBB18_4
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %edi, %eax
; X86-BMI1NOTBM-NEXT: .LBB18_4:
; X86-BMI1NOTBM-NEXT: decl %eax
; X86-BMI1NOTBM-NEXT: andl %esi, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_a3:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: je .LBB18_2
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edx
; X86-BMI1BMI2-NEXT: .LBB18_2:
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %bl
; X86-BMI1BMI2-NEXT: jne .LBB18_4
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl $1, %eax
; X86-BMI1BMI2-NEXT: shlxl %ebx, %eax, %eax
; X86-BMI1BMI2-NEXT: .LBB18_4:
; X86-BMI1BMI2-NEXT: decl %eax
; X86-BMI1BMI2-NEXT: andl %edx, %eax
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_a3:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: decl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_a3:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness Summary: Finally tying up loose ends here. The problem is quite simple: If we have pattern `(x >> start) & (1 << nbits) - 1`, and then truncate the result, that truncation will be propagated upwards, into the `and`. And that isn't currently handled. I'm only fixing pattern `a` here, the same fix will be needed for patterns `b`/`c` too. I *think* this isn't missing any extra legality checks, since we only look past truncations. Similary, i don't think we can get any other truncation there other than i64->i32. Reviewers: craig.topper, RKSimon, spatel Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62786 llvm-svn: 364417
2019-06-26 20:19:11 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_a3:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
[X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness Summary: Finally tying up loose ends here. The problem is quite simple: If we have pattern `(x >> start) & (1 << nbits) - 1`, and then truncate the result, that truncation will be propagated upwards, into the `and`. And that isn't currently handled. I'm only fixing pattern `a` here, the same fix will be needed for patterns `b`/`c` too. I *think* this isn't missing any extra legality checks, since we only look past truncations. Similary, i don't think we can get any other truncation there other than i64->i32. Reviewers: craig.topper, RKSimon, spatel Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62786 llvm-svn: 364417
2019-06-26 20:19:11 +08:00
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, 4294967295
%masked = and i64 %mask, %shifted
%truncmasked = trunc i64 %masked to i32
ret i32 %truncmasked
}
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; ---------------------------------------------------------------------------- ;
; Pattern b. 32-bit
; ---------------------------------------------------------------------------- ;
define i32 @bextr32_b0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_b0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_b0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_b0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_b0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_b0:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_b0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_b1_indexzext(i32 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_b1_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_b1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_b1_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_b1_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_b1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_b1_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%conv = zext i8 %numlowbits to i32
%notmask = shl i32 -1, %conv
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_b2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_b2_load:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_b2_load:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%eax), %eax
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_b2_load:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: shrxl %edx, (%ecx), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_b2_load:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl (%rdi), %esi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %esi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %esi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_b2_load:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, (%rdi), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_b2_load:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%shifted = lshr i32 %val, %numskipbits
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_b3_load_indexzext(i32* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_b3_load_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_b3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%eax), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_b3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: shrxl %edx, (%ecx), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_b3_load_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl (%rdi), %esi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %esi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %esi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_b3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, (%rdi), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_b3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%conv = zext i8 %numlowbits to i32
%notmask = shl i32 -1, %conv
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_b4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_b4_commutative:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_b4_commutative:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_b4_commutative:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_b4_commutative:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_b4_commutative:
; X64-BMI1NOTBM: # %bb.0:
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_b4_commutative:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %shifted, %mask ; swapped order
ret i32 %masked
}
define i32 @bextr32_b5_skipextrauses(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_b5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: notl %esi
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %eax, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_b5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl %al, %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %eax, (%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X86-BMI1NOTBM-NEXT: addl $8, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_b5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %esi
; X86-BMI1BMI2-NEXT: movl %ecx, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: addl $8, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_b5_skipextrauses:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: shrl %cl, %edi
; X64-NOBMI-NEXT: movl $-1, %ebx
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %ebx
; X64-NOBMI-NEXT: notl %ebx
; X64-NOBMI-NEXT: andl %edi, %ebx
; X64-NOBMI-NEXT: movl %esi, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: movl %ebx, %eax
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_b5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbx
[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ~(-1 << nbits) pattern Summary: As discussed in D48491, we can't really do this in the TableGen, since we need to produce *two* instructions. This only implements one single pattern. The other 3 patterns will be in follow-ups. I'm not sure yet if we want to also fuse shift into here (i.e `(x >> start) & ...`) Reviewers: RKSimon, craig.topper, spatel Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D52304 llvm-svn: 344224
2018-10-11 15:51:13 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: movl %ebx, %eax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_b5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %ebx
; X64-BMI1BMI2-NEXT: movl %esi, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %shifted
call void @use32(i32 %numskipbits)
ret i32 %masked
}
; 64-bit
define i64 @bextr64_b0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_b0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB25_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB25_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %edx
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: shldl %cl, %edx, %edx
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB25_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB25_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: notl %edx
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_b0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB25_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB25_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %edi
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %ebx
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB25_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %ebx, %edi
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB25_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %edi, %edx
; X86-BMI1NOTBM-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_b0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB25_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB25_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %edi
; X86-BMI1BMI2-NEXT: shlxl %eax, %edi, %ebx
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB25_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %edi
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB25_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %edi, %edx
; X86-BMI1BMI2-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_b0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: notq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_b0:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_b0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_b1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_b1_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB26_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB26_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %edx
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: shldl %cl, %edx, %edx
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB26_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB26_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: notl %edx
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_b1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB26_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB26_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %edi
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %ebx
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB26_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %ebx, %edi
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB26_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %edi, %edx
; X86-BMI1NOTBM-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_b1_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB26_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB26_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %edi
; X86-BMI1BMI2-NEXT: shlxl %eax, %edi, %ebx
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB26_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %edi
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB26_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %edi, %edx
; X86-BMI1BMI2-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_b1_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: notq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_b1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_b1_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: # kill: def $edx killed $edx def $rdx
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%conv = zext i8 %numlowbits to i64
%notmask = shl i64 -1, %conv
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_b2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_b2_load:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB27_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB27_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %edx
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: shldl %cl, %edx, %edx
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB27_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB27_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: notl %edx
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_b2_load:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl (%edx), %esi
; X86-BMI1NOTBM-NEXT: movl 4(%edx), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB27_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB27_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %edi
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %ebx
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB27_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %ebx, %edi
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB27_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %edi, %edx
; X86-BMI1NOTBM-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_b2_load:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl (%edx), %esi
; X86-BMI1BMI2-NEXT: movl 4(%edx), %edi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edi, %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB27_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB27_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %edi
; X86-BMI1BMI2-NEXT: shlxl %eax, %edi, %ebx
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB27_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %edi
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB27_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %edi, %edx
; X86-BMI1BMI2-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_b2_load:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq (%rdi), %rsi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rsi
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: notq %rax
; X64-NOBMI-NEXT: andq %rsi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_b2_load:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rdi), %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_b2_load:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%shifted = lshr i64 %val, %numskipbits
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_b3_load_indexzext(i64* %w, i8 zeroext %numskipbits, i8 zeroext %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_b3_load_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB28_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB28_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %edx
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: shldl %cl, %edx, %edx
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB28_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB28_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: notl %edx
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_b3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl (%edx), %esi
; X86-BMI1NOTBM-NEXT: movl 4(%edx), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB28_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB28_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %edi
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %ebx
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB28_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %ebx, %edi
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB28_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %edi, %edx
; X86-BMI1NOTBM-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_b3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl (%edx), %esi
; X86-BMI1BMI2-NEXT: movl 4(%edx), %edi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edi, %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB28_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB28_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %edi
; X86-BMI1BMI2-NEXT: shlxl %eax, %edi, %ebx
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB28_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %edi
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB28_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %edi, %edx
; X86-BMI1BMI2-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_b3_load_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movq (%rdi), %rsi
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrq %cl, %rsi
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: notq %rax
; X64-NOBMI-NEXT: andq %rsi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_b3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rdi), %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_b3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: # kill: def $edx killed $edx def $rdx
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%conv = zext i8 %numlowbits to i64
%notmask = shl i64 -1, %conv
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_b4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_b4_commutative:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %edx
; X86-NOBMI-NEXT: shrl %cl, %edx
; X86-NOBMI-NEXT: shrdl %cl, %esi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB29_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB29_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %edi
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: movb %ch, %cl
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: shldl %cl, %edi, %edi
; X86-NOBMI-NEXT: testb $32, %ch
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB29_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB29_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: notl %edi
; X86-NOBMI-NEXT: andl %edi, %edx
; X86-NOBMI-NEXT: notl %esi
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_b4_commutative:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB29_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB29_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %edi
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %ebx
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB29_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %ebx, %edi
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB29_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %edi, %edx
; X86-BMI1NOTBM-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_b4_commutative:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB29_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB29_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %edi
; X86-BMI1BMI2-NEXT: shlxl %eax, %edi, %ebx
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB29_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %edi
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB29_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %edi, %edx
; X86-BMI1BMI2-NEXT: andnl %esi, %ebx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_b4_commutative:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: notq %rax
; X64-NOBMI-NEXT: andq %rdi, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_b4_commutative:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_b4_commutative:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %shifted, %mask ; swapped order
ret i64 %masked
}
define i64 @bextr64_b5_skipextrauses(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_b5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: subl $12, %esp
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %esi, %ebp
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: shrl %cl, %ebp
; X86-NOBMI-NEXT: shrdl %cl, %esi, %ebx
; X86-NOBMI-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB30_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %ebp, %ebx
; X86-NOBMI-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB30_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: movl $-1, %edi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: shldl %cl, %esi, %esi
; X86-NOBMI-NEXT: testb $32, %dl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB30_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB30_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: notl %esi
; X86-NOBMI-NEXT: andl %ebp, %esi
; X86-NOBMI-NEXT: notl %edi
; X86-NOBMI-NEXT: andl %ebx, %edi
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NOBMI-NEXT: pushl %eax
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: movl %edi, %eax
; X86-NOBMI-NEXT: movl %esi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_b5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: subl $12, %esp
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %ebx, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebx, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB30_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB30_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: movl %edx, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %ebp
; X86-BMI1NOTBM-NEXT: shldl %cl, %ebx, %ebx
; X86-BMI1NOTBM-NEXT: testb $32, %dl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB30_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %ebp, %ebx
; X86-BMI1NOTBM-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB30_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %esi, %ebx, %esi
; X86-BMI1NOTBM-NEXT: andnl %edi, %ebp, %edi
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl {{[0-9]+}}(%esp)
; X86-BMI1NOTBM-NEXT: pushl %eax
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: movl %edi, %eax
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_b5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: subl $12, %esp
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edi
; X86-BMI1BMI2-NEXT: shrxl %eax, %esi, %esi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB30_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %esi, %edi
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB30_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebp
; X86-BMI1BMI2-NEXT: shlxl %edx, %ebp, %ebx
; X86-BMI1BMI2-NEXT: movl %edx, %ecx
; X86-BMI1BMI2-NEXT: shldl %cl, %ebp, %ebp
; X86-BMI1BMI2-NEXT: testb $32, %dl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB30_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %ebp
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB30_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %esi, %ebp, %esi
; X86-BMI1BMI2-NEXT: andnl %edi, %ebx, %edi
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl {{[0-9]+}}(%esp)
; X86-BMI1BMI2-NEXT: pushl %eax
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: movl %edi, %eax
; X86-BMI1BMI2-NEXT: movl %esi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_b5_skipextrauses:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movq $-1, %rbx
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rbx
; X64-NOBMI-NEXT: notq %rbx
; X64-NOBMI-NEXT: andq %rdi, %rbx
; X64-NOBMI-NEXT: movq %rsi, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_b5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbx
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movq %rsi, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_b5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rbx
; X64-BMI1BMI2-NEXT: movq %rsi, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: movq %rbx, %rax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %shifted
call void @use64(i64 %numskipbits)
ret i64 %masked
}
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; 64-bit, but with 32-bit output
; Everything done in 64-bit, truncation happens last.
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @bextr64_32_b0(i64 %val, i64 %numskipbits, i8 %numlowbits) nounwind {
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-LABEL: bextr64_32_b0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %edi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB31_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB31_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: testb $32, %dl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB31_4
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB31_4:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: notl %ecx
; X86-NOBMI-NEXT: andl %ecx, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_b0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB31_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB31_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %esi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB31_4
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB31_4:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %ecx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_b0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB31_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB31_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: xorl %ecx, %ecx
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB31_4
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shlxl %eax, %ecx, %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB31_4:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %ecx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_b0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_b0:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness Summary: (Not so) boringly identical to pattern a (D62786) Not yet sure how do deal with the last pattern c. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62793 llvm-svn: 364418
2019-06-26 20:19:39 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_b0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
[X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness Summary: (Not so) boringly identical to pattern a (D62786) Not yet sure how do deal with the last pattern c. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62793 llvm-svn: 364418
2019-06-26 20:19:39 +08:00
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X64-BMI1BMI2-NEXT: retq
%shiftedval = lshr i64 %val, %numskipbits
%widenumlowbits = zext i8 %numlowbits to i64
%notmask = shl nsw i64 -1, %widenumlowbits
%mask = xor i64 %notmask, -1
%wideres = and i64 %shiftedval, %mask
%res = trunc i64 %wideres to i32
ret i32 %res
}
; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @bextr64_32_b1(i64 %val, i64 %numskipbits, i8 %numlowbits) nounwind {
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-LABEL: bextr64_32_b1:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: shrdl %cl, %edi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB32_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB32_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_b1:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB32_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB32_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_b1:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB32_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB32_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_b1:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_b1:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_b1:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shiftedval = lshr i64 %val, %numskipbits
%truncshiftedval = trunc i64 %shiftedval to i32
%widenumlowbits = zext i8 %numlowbits to i32
%notmask = shl nsw i32 -1, %widenumlowbits
%mask = xor i32 %notmask, -1
%res = and i32 %truncshiftedval, %mask
ret i32 %res
}
; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
; Masking is 64-bit. Then truncation.
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @bextr64_32_b2(i64 %val, i64 %numskipbits, i8 %numlowbits) nounwind {
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-LABEL: bextr64_32_b2:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: shrdl %cl, %edi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB33_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB33_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: notl %eax
; X86-NOBMI-NEXT: andl %esi, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_b2:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB33_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB33_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_b2:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB33_2
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB33_2:
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_b2:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $-1, %eax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: notl %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_b2:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419) @bextr64_32_b1 is extracted from hotpath of real-world code (RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`. @bextr64_32_b2/@bextr64_32_b0 is the same pattern, but with trunc done last, showing how i think it can be handled: https://rise4fun.com/Alive/K4B https://rise4fun.com/Alive/qC9 It is possible that middle-end should do some of this, too. https://bugs.llvm.org/show_bug.cgi?id=36419 llvm-svn: 349998
2018-12-22 17:40:14 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_b2:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shiftedval = lshr i64 %val, %numskipbits
%widenumlowbits = zext i8 %numlowbits to i32
%notmask = shl nsw i32 -1, %widenumlowbits
%mask = xor i32 %notmask, -1
%zextmask = zext i32 %mask to i64
%wideres = and i64 %shiftedval, %zextmask
%res = trunc i64 %wideres to i32
ret i32 %res
}
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; Shifting happens in 64-bit. Mask is 32-bit, but calculated in 64-bit.
; Masking is 64-bit. Then truncation.
define i32 @bextr64_32_b3(i64 %val, i64 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_b3:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl %edi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %edi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB34_2
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB34_2:
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: movl %edx, %ecx
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: testb $32, %dl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB34_4
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB34_4:
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-NOBMI-NEXT: notl %ecx
; X86-NOBMI-NEXT: andl %ecx, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_b3:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB34_2
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB34_2:
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shll %cl, %esi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB34_4
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB34_4:
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1NOTBM-NEXT: andnl %edx, %ecx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_b3:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB34_2
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB34_2:
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1BMI2-NEXT: xorl %ecx, %ecx
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB34_4
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shlxl %eax, %ecx, %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB34_4:
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X86-BMI1BMI2-NEXT: andnl %edx, %ecx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_b3:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
; X64-NOBMI-NEXT: movl $4294967295, %esi # imm = 0xFFFFFFFF
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rsi
; X64-NOBMI-NEXT: xorl %esi, %eax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_b3:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness Summary: (Not so) boringly identical to pattern a (D62786) Not yet sure how do deal with the last pattern c. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62793 llvm-svn: 364418
2019-06-26 20:19:39 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_b3:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
[X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness Summary: (Not so) boringly identical to pattern a (D62786) Not yet sure how do deal with the last pattern c. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62793 llvm-svn: 364418
2019-06-26 20:19:39 +08:00
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
[NFC][X86] extract-lowbits.ll: add one more pattern a with truncation We are also free to interpret this as 'BZHI'/'BEXTR'. https://rise4fun.com/Alive/dD6 llvm-svn: 362325
2019-06-02 23:07:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shiftedval = lshr i64 %val, %numskipbits
%widenumlowbits = zext i8 %numlowbits to i64
%notmask = shl nsw i64 4294967295, %widenumlowbits
%mask = xor i64 %notmask, 4294967295
%wideres = and i64 %shiftedval, %mask
%res = trunc i64 %wideres to i32
ret i32 %res
}
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; ---------------------------------------------------------------------------- ;
; Pattern c. 32-bit
; ---------------------------------------------------------------------------- ;
define i32 @bextr32_c0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_c0:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_c0:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: pushl %eax
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: andl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $4, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_c0:
; X86-BMI1BMI2: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: pushl %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: shrxl %eax, {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %eax
; X86-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shrxl %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: movl %eax, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: addl $4, %esp
; X86-BMI1BMI2-NEXT: popl %esi
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_c0:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl $-1, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebp
; X64-NOBMI-NEXT: movl %ebp, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: andl %ebx, %ebp
; X64-NOBMI-NEXT: movl %ebp, %eax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_c0:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl $-1, %ebp
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebp
; X64-BMI1NOTBM-NEXT: movl %ebp, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: andl %ebx, %ebp
; X64-BMI1NOTBM-NEXT: movl %ebp, %eax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_c0:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movl $-1, %ecx
; X64-BMI1BMI2-NEXT: shrxl %eax, %ecx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebx, %ebp, %eax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use32(i32 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_c1_indexzext(i32 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_c1_indexzext:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_c1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: andl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $4, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_c1_indexzext:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: pushl %eax
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: shrxl %eax, {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %eax
; X86-BMI1BMI2-NEXT: negb %al
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shrxl %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: movl %eax, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %eax
; X86-BMI1BMI2-NEXT: addl $4, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_c1_indexzext:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl $-1, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebp
; X64-NOBMI-NEXT: movl %ebp, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: andl %ebx, %ebp
; X64-NOBMI-NEXT: movl %ebp, %eax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_c1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movl $-1, %ebp
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebp
; X64-BMI1NOTBM-NEXT: movl %ebp, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: andl %ebx, %ebp
; X64-BMI1NOTBM-NEXT: movl %ebp, %eax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_c1_indexzext:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %ebp
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
; X64-BMI1BMI2-NEXT: movl $-1, %ecx
; X64-BMI1BMI2-NEXT: shrxl %eax, %ecx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebx, %ebp, %eax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%mask = lshr i32 -1, %sh_prom
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use32(i32 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_c2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_c2_load:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl (%eax), %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_c2_load:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: pushl %eax
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: andl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $4, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_c2_load:
; X86-BMI1BMI2: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: pushl %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: shrxl %ecx, (%eax), %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %eax
; X86-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shrxl %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: movl %eax, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: addl $4, %esp
; X86-BMI1BMI2-NEXT: popl %esi
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_c2_load:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl (%rdi), %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl $-1, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebx
; X64-NOBMI-NEXT: movl %ebx, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: andl %ebp, %ebx
; X64-NOBMI-NEXT: movl %ebx, %eax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_c2_load:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl (%rdi), %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl $-1, %ebx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X64-BMI1NOTBM-NEXT: movl %ebx, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: andl %ebp, %ebx
; X64-BMI1NOTBM-NEXT: movl %ebx, %eax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_c2_load:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movl $-1, %ecx
; X64-BMI1BMI2-NEXT: shrxl %eax, %ecx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebx, %ebp, %eax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use32(i32 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_c3_load_indexzext(i32* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_c3_load_indexzext:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl (%eax), %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_c3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: andl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $4, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_c3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: pushl %eax
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, (%eax), %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %eax
; X86-BMI1BMI2-NEXT: negb %al
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shrxl %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: movl %eax, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %eax
; X86-BMI1BMI2-NEXT: addl $4, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_c3_load_indexzext:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl (%rdi), %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl $-1, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebx
; X64-NOBMI-NEXT: movl %ebx, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: andl %ebp, %ebx
; X64-NOBMI-NEXT: movl %ebx, %eax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_c3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl (%rdi), %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebp
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movl $-1, %ebx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X64-BMI1NOTBM-NEXT: movl %ebx, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: andl %ebp, %ebx
; X64-BMI1NOTBM-NEXT: movl %ebx, %eax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_c3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %ebp
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
; X64-BMI1BMI2-NEXT: movl $-1, %ecx
; X64-BMI1BMI2-NEXT: shrxl %eax, %ecx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebx, %ebp, %eax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%mask = lshr i32 -1, %sh_prom
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use32(i32 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i32 %mask, %shifted
ret i32 %masked
}
define i32 @bextr32_c4_commutative(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_c4_commutative:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: pushl %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $4, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_c4_commutative:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: pushl %eax
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: andl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $4, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_c4_commutative:
; X86-BMI1BMI2: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: pushl %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: shrxl %eax, {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %eax
; X86-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shrxl %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: movl %eax, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: addl $4, %esp
; X86-BMI1BMI2-NEXT: popl %esi
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_c4_commutative:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl $-1, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrl %cl, %ebp
; X64-NOBMI-NEXT: movl %ebp, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: andl %ebx, %ebp
; X64-NOBMI-NEXT: movl %ebp, %eax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_c4_commutative:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl $-1, %ebp
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebp
; X64-BMI1NOTBM-NEXT: movl %ebp, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: andl %ebx, %ebp
; X64-BMI1NOTBM-NEXT: movl %ebp, %eax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_c4_commutative:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movl $-1, %ecx
; X64-BMI1BMI2-NEXT: shrxl %eax, %ecx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebx, %ebp, %eax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use32(i32 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i32 %shifted, %mask ; swapped order
ret i32 %masked
}
define i32 @bextr32_c5_skipextrauses(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_c5_skipextrauses:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $16, %esp
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NOBMI-NEXT: movl %ebx, %ecx
; X86-NOBMI-NEXT: shrl %cl, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %esi, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: andl %edi, %esi
; X86-NOBMI-NEXT: movl %ebx, (%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: movl %esi, %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: addl $16, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_c5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $16, %esp
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BMI1NOTBM-NEXT: movl %ebx, %ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: movl %esi, (%esp)
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: andl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %ebx, (%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: addl $16, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_c5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $16, %esp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %bl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edi
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: shrxl %edi, {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl %ebx, %eax
; X86-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ecx
; X86-BMI1BMI2-NEXT: shrxl %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: movl %eax, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: bzhil %ebx, %esi, %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %edi, (%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: movl %esi, %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: addl $16, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_c5_skipextrauses:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %rbp
; X64-NOBMI-NEXT: pushq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: pushq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl %esi, %r14d
; X64-NOBMI-NEXT: movl %edi, %ebp
; X64-NOBMI-NEXT: movl %r14d, %ecx
; X64-NOBMI-NEXT: shrl %cl, %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl $-1, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shrl %cl, %ebx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movl %ebx, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: andl %ebp, %ebx
; X64-NOBMI-NEXT: movl %r14d, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: movl %ebx, %eax
; X64-NOBMI-NEXT: popq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: popq %r14
; X64-NOBMI-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_c5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbp
; X64-BMI1NOTBM-NEXT: pushq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: pushq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %r14d
; X64-BMI1NOTBM-NEXT: movl %edi, %ebp
; X64-BMI1NOTBM-NEXT: movl %r14d, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movl $-1, %ebx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X64-BMI1NOTBM-NEXT: movl %ebx, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: andl %ebp, %ebx
; X64-BMI1NOTBM-NEXT: movl %r14d, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: movl %ebx, %eax
; X64-BMI1NOTBM-NEXT: popq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: popq %r14
; X64-BMI1NOTBM-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_c5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbp
; X64-BMI1BMI2-NEXT: pushq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: pushq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
; X64-BMI1BMI2-NEXT: movl %esi, %ebp
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %r14d
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movl $-1, %ecx
; X64-BMI1BMI2-NEXT: shrxl %eax, %ecx, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: bzhil %ebx, %r14d, %ebx
; X64-BMI1BMI2-NEXT: movl %ebp, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: popq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: popq %r14
; X64-BMI1BMI2-NEXT: popq %rbp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use32(i32 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i32 %mask, %shifted
call void @use32(i32 %numskipbits)
ret i32 %masked
}
; 64-bit
define i64 @bextr64_c0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_c0:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB41_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB41_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %ebp
; X86-NOBMI-NEXT: movl $-1, %ebx
; X86-NOBMI-NEXT: shrl %cl, %ebx
; X86-NOBMI-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB41_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %ebx, %ebp
; X86-NOBMI-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB41_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: andl %ebp, %esi
; X86-NOBMI-NEXT: andl %ebx, %edi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_c0:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB41_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB41_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB41_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %ebp
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB41_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: andl %ebp, %esi
; X86-BMI1NOTBM-NEXT: andl %ebx, %edi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_c0:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB41_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB41_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %ebx, %ebp
; X86-BMI1BMI2-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB41_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %ebp, %ebx
; X86-BMI1BMI2-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB41_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: andl %ebx, %esi
; X86-BMI1BMI2-NEXT: andl %ebp, %edi
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_c0:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %r14
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movq %rsi, %rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq %rdi, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %r14
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq $-1, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: andq %r14, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_c0:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %r14
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq %rdi, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrq %cl, %r14
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq $-1, %rbx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: andq %r14, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_c0:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %r14
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movq %rdx, %rbx
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %r14
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movq $-1, %rcx
; X64-BMI1BMI2-NEXT: shrxq %rax, %rcx, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: bzhiq %rbx, %r14, %rax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use64(i64 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_c1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_c1_indexzext:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB42_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB42_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %ebp
; X86-NOBMI-NEXT: movl $-1, %ebx
; X86-NOBMI-NEXT: shrl %cl, %ebx
; X86-NOBMI-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB42_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %ebx, %ebp
; X86-NOBMI-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB42_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: andl %ebp, %esi
; X86-NOBMI-NEXT: andl %ebx, %edi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_c1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB42_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB42_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB42_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %ebp
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB42_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: andl %ebp, %esi
; X86-BMI1NOTBM-NEXT: andl %ebx, %edi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_c1_indexzext:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB42_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB42_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %ebx, %ebp
; X86-BMI1BMI2-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB42_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %ebp, %ebx
; X86-BMI1BMI2-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB42_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: andl %ebx, %esi
; X86-BMI1BMI2-NEXT: andl %ebp, %edi
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_c1_indexzext:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %r14
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq %rdi, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq $-1, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: andq %r14, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_c1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %r14
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq %rdi, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrq %cl, %r14
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movq $-1, %rbx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: andq %r14, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_c1_indexzext:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %r14
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %r14
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
; X64-BMI1BMI2-NEXT: movq $-1, %rcx
; X64-BMI1BMI2-NEXT: shrxq %rax, %rcx, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: bzhiq %rbx, %r14, %rax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%mask = lshr i64 -1, %sh_prom
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use64(i64 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_c2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_c2_load:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB43_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB43_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %ebp
; X86-NOBMI-NEXT: movl $-1, %ebx
; X86-NOBMI-NEXT: shrl %cl, %ebx
; X86-NOBMI-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB43_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %ebx, %ebp
; X86-NOBMI-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB43_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: andl %ebp, %esi
; X86-NOBMI-NEXT: andl %ebx, %edi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_c2_load:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %esi
; X86-BMI1NOTBM-NEXT: movl 4(%eax), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB43_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB43_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB43_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %ebp
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB43_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: andl %ebp, %esi
; X86-BMI1NOTBM-NEXT: andl %ebx, %edi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_c2_load:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl (%eax), %esi
; X86-BMI1BMI2-NEXT: movl 4(%eax), %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB43_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB43_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %ebx, %ebp
; X86-BMI1BMI2-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB43_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %ebp, %ebx
; X86-BMI1BMI2-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB43_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: andl %ebx, %esi
; X86-BMI1BMI2-NEXT: andl %ebp, %edi
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_c2_load:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %r14
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movq %rsi, %rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq (%rdi), %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %r14
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq $-1, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: andq %r14, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_c2_load:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %r14
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq (%rdi), %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrq %cl, %r14
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq $-1, %rbx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: andq %r14, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_c2_load:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %r14
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movq %rdx, %rbx
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %r14
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movq $-1, %rcx
; X64-BMI1BMI2-NEXT: shrxq %rax, %rcx, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: bzhiq %rbx, %r14, %rax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use64(i64 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_c3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_c3_load_indexzext:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %esi
; X86-NOBMI-NEXT: movl 4(%eax), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB44_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB44_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %ebp
; X86-NOBMI-NEXT: movl $-1, %ebx
; X86-NOBMI-NEXT: shrl %cl, %ebx
; X86-NOBMI-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB44_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %ebx, %ebp
; X86-NOBMI-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB44_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: andl %ebp, %esi
; X86-NOBMI-NEXT: andl %ebx, %edi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_c3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %esi
; X86-BMI1NOTBM-NEXT: movl 4(%eax), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB44_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB44_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB44_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %ebp
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB44_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: andl %ebp, %esi
; X86-BMI1NOTBM-NEXT: andl %ebx, %edi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_c3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl (%eax), %esi
; X86-BMI1BMI2-NEXT: movl 4(%eax), %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB44_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB44_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %ebx, %ebp
; X86-BMI1BMI2-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB44_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %ebp, %ebx
; X86-BMI1BMI2-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB44_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: andl %ebx, %esi
; X86-BMI1BMI2-NEXT: andl %ebp, %edi
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_c3_load_indexzext:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %r14
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq (%rdi), %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq $-1, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: andq %r14, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_c3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %r14
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq (%rdi), %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrq %cl, %r14
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movq $-1, %rbx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: andq %r14, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_c3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %r14
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movl %edx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %r14
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
; X64-BMI1BMI2-NEXT: movq $-1, %rcx
; X64-BMI1BMI2-NEXT: shrxq %rax, %rcx, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: bzhiq %rbx, %r14, %rax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%mask = lshr i64 -1, %sh_prom
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use64(i64 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i64 %mask, %shifted
ret i64 %masked
}
define i64 @bextr64_c4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_c4_commutative:
; X86-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB45_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB45_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %ebp
; X86-NOBMI-NEXT: movl $-1, %ebx
; X86-NOBMI-NEXT: shrl %cl, %ebx
; X86-NOBMI-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB45_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %ebx, %ebp
; X86-NOBMI-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB45_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: andl %ebp, %esi
; X86-NOBMI-NEXT: andl %ebx, %edi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_c4_commutative:
; X86-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB45_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB45_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB45_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %ebp
; X86-BMI1NOTBM-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB45_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: andl %ebp, %esi
; X86-BMI1NOTBM-NEXT: andl %ebx, %edi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_c4_commutative:
; X86-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB45_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB45_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %ebx, %ebp
; X86-BMI1BMI2-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB45_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %ebp, %ebx
; X86-BMI1BMI2-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB45_4:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: andl %ebx, %esi
; X86-BMI1BMI2-NEXT: andl %ebp, %edi
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_c4_commutative:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %r14
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movq %rsi, %rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq %rdi, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %r14
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq $-1, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: andq %r14, %rbx
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: addq $8, %rsp
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_c4_commutative:
; X64-BMI1NOTBM: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: pushq %r14
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: pushq %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq %rdi, %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: shrq %cl, %r14
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1NOTBM-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1NOTBM-NEXT: movq $-1, %rbx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: andq %r14, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: addq $8, %rsp
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_c4_commutative:
; X64-BMI1BMI2: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: pushq %r14
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: pushq %rax
; X64-BMI1BMI2-NEXT: movq %rdx, %rbx
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %r14
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-BMI1BMI2-NEXT: negb %al
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-BMI1BMI2-NEXT: movq $-1, %rcx
; X64-BMI1BMI2-NEXT: shrxq %rax, %rcx, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: bzhiq %rbx, %r14, %rax
; X64-BMI1BMI2-NEXT: addq $8, %rsp
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
call void @use64(i64 %mask)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%masked = and i64 %shifted, %mask ; swapped order
ret i64 %masked
}
define i64 @bextr64_c5_skipextrauses(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_c5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: subl $12, %esp
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: shrl %cl, %edi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB46_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB46_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl $-1, %ebx
; X86-NOBMI-NEXT: movl $-1, %ebp
; X86-NOBMI-NEXT: shrl %cl, %ebp
; X86-NOBMI-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: je .LBB46_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: movl %ebp, %ebx
; X86-NOBMI-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB46_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ebp
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: andl %ebx, %esi
; X86-NOBMI-NEXT: andl %ebp, %edi
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NOBMI-NEXT: pushl {{[0-9]+}}(%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_c5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: subl $12, %esp
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: shrl %cl, %edi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB46_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB46_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl $-1, %ebx
; X86-BMI1NOTBM-NEXT: movl $-1, %ebp
; X86-BMI1NOTBM-NEXT: shrl %cl, %ebp
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebx, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB46_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebp, %ebx
; X86-BMI1NOTBM-NEXT: xorl %ebp, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB46_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ebp
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: andl %ebx, %esi
; X86-BMI1NOTBM-NEXT: andl %ebp, %edi
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl {{[0-9]+}}(%esp)
; X86-BMI1NOTBM-NEXT: pushl {{[0-9]+}}(%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_c5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebp
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: subl $12, %esp
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB46_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: xorl %edi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB46_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl $-1, %ebp
; X86-BMI1BMI2-NEXT: shrxl %ecx, %ebp, %ebx
; X86-BMI1BMI2-NEXT: shrdl %cl, %ebp, %ebp
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB46_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: movl %ebx, %ebp
; X86-BMI1BMI2-NEXT: xorl %ebx, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB46_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: pushl %ebp
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: andl %ebp, %esi
; X86-BMI1BMI2-NEXT: andl %ebx, %edi
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl {{[0-9]+}}(%esp)
; X86-BMI1BMI2-NEXT: pushl {{[0-9]+}}(%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: movl %edi, %edx
; X86-BMI1BMI2-NEXT: addl $12, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: popl %ebp
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_c5_skipextrauses:
; X64-NOBMI: # %bb.0:
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: pushq %r15
; X64-NOBMI-NEXT: pushq %r14
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: pushq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq %rsi, %r14
; X64-NOBMI-NEXT: movq %rdi, %r15
; X64-NOBMI-NEXT: movl %r14d, %ecx
; X64-NOBMI-NEXT: shrq %cl, %r15
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq $-1, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shrq %cl, %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: movq %rbx, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: andq %r15, %rbx
; X64-NOBMI-NEXT: movq %r14, %rdi
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: popq %rbx
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests Summary: Because of the D48768, that pattern is always unfolded into pattern d, thus we had no test coverage. Reviewers: RKSimon, craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53574 llvm-svn: 345583
2018-10-30 19:12:29 +08:00
; X64-NOBMI-NEXT: popq %r14
; X64-NOBMI-NEXT: popq %r15
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-LABEL: bextr64_c5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %r15
; X64-BMI1NOTBM-NEXT: pushq %r14
; X64-BMI1NOTBM-NEXT: pushq %rbx
; X64-BMI1NOTBM-NEXT: movq %rsi, %r14
; X64-BMI1NOTBM-NEXT: movq %rdi, %r15
; X64-BMI1NOTBM-NEXT: movl %r14d, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %r15
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movq $-1, %rbx
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rbx
; X64-BMI1NOTBM-NEXT: movq %rbx, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: andq %r15, %rbx
; X64-BMI1NOTBM-NEXT: movq %r14, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: popq %r14
; X64-BMI1NOTBM-NEXT: popq %r15
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_c5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %r15
; X64-BMI1BMI2-NEXT: pushq %r14
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: movq %rdx, %rbx
; X64-BMI1BMI2-NEXT: movq %rsi, %r14
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %r15
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: negb %al
; X64-BMI1BMI2-NEXT: movq $-1, %rcx
; X64-BMI1BMI2-NEXT: shrxq %rax, %rcx, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: bzhiq %rbx, %r15, %rbx
; X64-BMI1BMI2-NEXT: movq %r14, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: movq %rbx, %rax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: popq %r14
; X64-BMI1BMI2-NEXT: popq %r15
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
call void @use64(i64 %mask)
%masked = and i64 %mask, %shifted
call void @use64(i64 %numskipbits)
ret i64 %masked
}
; 64-bit, but with 32-bit output
; Everything done in 64-bit, truncation happens last.
define i32 @bextr64_32_c0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_c0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %edx
; X86-NOBMI-NEXT: shrl %cl, %edx
; X86-NOBMI-NEXT: shrdl %cl, %esi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB47_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB47_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: movl $-1, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %esi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB47_4
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB47_4:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: andl %edx, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_c0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %esi, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB47_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB47_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: movl $-1, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: shrdl %cl, %esi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB47_4
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB47_4:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: andl %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_c0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB47_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB47_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl $-1, %esi
; X86-BMI1BMI2-NEXT: movl $-1, %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB47_4
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB47_4:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: andl %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_c0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movq $-1, %rax
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_c0:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness Summary: The one thing of note here is that the 'bitwidth' constant (32/64) was previously pessimistic. Given `x & (-1 >> (C - z))`, we were taking `C` to be `bitwidth(x)`, but in reality we want `(-1 >> (C - z))` pattern to mean "low z bits must be all-ones". And for that, `C` should be `bitwidth(-1 >> (C - z))`, i.e. of the shift operation itself. Last pattern D does not seem to exhibit any of these truncation issues. Although it has the opposite problem - if we extract low bits (no shift) from i64, and then truncate to i32, then we fail to shrink this 64-bit extraction into 32-bit extraction. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62806 llvm-svn: 364419
2019-06-26 20:19:47 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_c0:
; X64-BMI1BMI2: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness Summary: The one thing of note here is that the 'bitwidth' constant (32/64) was previously pessimistic. Given `x & (-1 >> (C - z))`, we were taking `C` to be `bitwidth(x)`, but in reality we want `(-1 >> (C - z))` pattern to mean "low z bits must be all-ones". And for that, `C` should be `bitwidth(-1 >> (C - z))`, i.e. of the shift operation itself. Last pattern D does not seem to exhibit any of these truncation issues. Although it has the opposite problem - if we extract low bits (no shift) from i64, and then truncate to i32, then we fail to shrink this 64-bit extraction into 32-bit extraction. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62806 llvm-svn: 364419
2019-06-26 20:19:47 +08:00
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
%masked = and i64 %mask, %shifted
%res = trunc i64 %masked to i32
ret i32 %res
}
; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
define i32 @bextr64_32_c1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_c1:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %esi, %edx
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB48_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edx, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB48_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_c1:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB48_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB48_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_c1:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB48_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB48_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_c1:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_c1:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_c1:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%truncshifted = trunc i64 %shifted to i32
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
%masked = and i32 %mask, %truncshifted
ret i32 %masked
}
; Shifting happens in 64-bit. Mask is 32-bit, but extended to 64-bit.
; Masking is 64-bit. Then truncation.
define i32 @bextr64_32_c2(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_c2:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %esi, %edx
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: jne .LBB49_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edx, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-NOBMI-NEXT: .LBB49_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_c2:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB49_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1NOTBM-NEXT: .LBB49_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_c2:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: je .LBB49_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern a with truncation llvm-svn: 362330
2019-06-03 01:11:21 +08:00
; X86-BMI1BMI2-NEXT: .LBB49_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_c2:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_c2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-LABEL: bextr64_32_c2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2: # %bb.0:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
%zextmask = zext i32 %mask to i64
%masked = and i64 %zextmask, %shifted
%truncmasked = trunc i64 %masked to i32
ret i32 %truncmasked
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
}
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; Shifting happens in 64-bit. Mask is 32-bit, but calculated in 64-bit.
; Masking is 64-bit. Then truncation.
define i32 @bextr64_32_c3(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_c3:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %edx
; X86-NOBMI-NEXT: shrl %cl, %edx
; X86-NOBMI-NEXT: shrdl %cl, %esi, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB50_2
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: .LBB50_2:
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: xorl %eax, %eax
; X86-NOBMI-NEXT: movl $-1, %esi
; X86-NOBMI-NEXT: shrdl %cl, %eax, %esi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: jne .LBB50_4
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: .LBB50_4:
; X86-NOBMI-NEXT: andl %edx, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_c3:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %esi, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: jne .LBB50_2
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: .LBB50_2:
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
; X86-BMI1NOTBM-NEXT: movl $-1, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: jne .LBB50_4
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: .LBB50_4:
; X86-BMI1NOTBM-NEXT: andl %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_c3:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: je .LBB50_2
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %eax, %edx
; X86-BMI1BMI2-NEXT: .LBB50_2:
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
; X86-BMI1BMI2-NEXT: movl $-1, %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: jne .LBB50_4
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: .LBB50_4:
; X86-BMI1BMI2-NEXT: andl %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_c3:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rdi
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: andl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_c3:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rdi
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rax
; X64-BMI1NOTBM-NEXT: andl %edi, %eax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_c3:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rcx
; X64-BMI1BMI2-NEXT: negb %dl
; X64-BMI1BMI2-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
; X64-BMI1BMI2-NEXT: shrxq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: andl %ecx, %eax
; X64-BMI1BMI2-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 4294967295, %numhighbits
%masked = and i64 %mask, %shifted
%truncmasked = trunc i64 %masked to i32
ret i32 %truncmasked
}
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; ---------------------------------------------------------------------------- ;
; Pattern d. 32-bit.
; ---------------------------------------------------------------------------- ;
define i32 @bextr32_d0(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_d0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_d0:
; X86-BMI1NOTBM: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
[DAGCombiner] disable truncation of binops by default As discussed in the post-commit thread of r347917, this transform is fighting with an existing transform causing an infinite loop or out-of-memory, so this is effectively reverting r347917 and its follow-up r348195 while we investigate the bug. llvm-svn: 348604
2018-12-07 23:47:52 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_d0:
; X86-BMI1BMI2: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_d0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_d0:
; X64-BMI1NOTBM: # %bb.0:
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_d0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%highbitscleared = shl i32 %shifted, %numhighbits
%masked = lshr i32 %highbitscleared, %numhighbits
ret i32 %masked
}
define i32 @bextr32_d1_indexzext(i32 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_d1_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_d1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: shll $8, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: orl %eax, %ecx
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_d1_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_d1_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl %edi, %eax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_d1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_d1_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%highbitscleared = shl i32 %shifted, %sh_prom
%masked = lshr i32 %highbitscleared, %sh_prom
ret i32 %masked
}
define i32 @bextr32_d2_load(i32* %w, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_d2_load:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_d2_load:
; X86-BMI1NOTBM: # %bb.0:
Revert "[X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern" *Seems* to be breaking sanitizer-x86_64-linux-fast buildbot, the ELF/relocatable-versioned.s test: ==17758==MemorySanitizer CHECK failed: /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_allocator.cc:191 "((kBlockMagic)) == ((((u64*)addr)[0]))" (0x6a6cb03abcebc041, 0x0) #0 0x59716b in MsanCheckFailed(char const*, int, char const*, unsigned long long, unsigned long long) /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/msan/msan.cc:393 #1 0x586635 in __sanitizer::CheckFailed(char const*, int, char const*, unsigned long long, unsigned long long) /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_termination.cc:79 #2 0x57d5ff in __sanitizer::InternalFree(void*, __sanitizer::SizeClassAllocatorLocalCache<__sanitizer::SizeClassAllocator32<__sanitizer::AP32> >*) /b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_allocator.cc:191 #3 0x7fc21b24193f (/lib/x86_64-linux-gnu/libc.so.6+0x3593f) #4 0x7fc21b241999 in exit (/lib/x86_64-linux-gnu/libc.so.6+0x35999) #5 0x7fc21b22c2e7 in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x202e7) #6 0x57c039 in _start (/b/sanitizer-x86_64-linux-fast/build/llvm_build_msan/bin/lld+0x57c039) This reverts commit r345014. llvm-svn: 345017
2018-10-23 18:34:57 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[DAGCombiner] disable truncation of binops by default As discussed in the post-commit thread of r347917, this transform is fighting with an existing transform causing an infinite loop or out-of-memory, so this is effectively reverting r347917 and its follow-up r348195 while we investigate the bug. llvm-svn: 348604
2018-12-07 23:47:52 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%eax), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_d2_load:
; X86-BMI1BMI2: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: shrxl %edx, (%ecx), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_d2_load:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl (%rdi), %eax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %eax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_d2_load:
; X64-BMI1NOTBM: # %bb.0:
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, (%rdi), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_d2_load:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%highbitscleared = shl i32 %shifted, %numhighbits
%masked = lshr i32 %highbitscleared, %numhighbits
ret i32 %masked
}
define i32 @bextr32_d3_load_indexzext(i32* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_d3_load_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_d3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%eax), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_d3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-BMI1BMI2-NEXT: shrxl %edx, (%ecx), %ecx
; X86-BMI1BMI2-NEXT: bzhil %eax, %ecx, %eax
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_d3_load_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movl (%rdi), %eax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_d3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, (%rdi), %eax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_d3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxl %esi, (%rdi), %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%val = load i32, i32* %w
%skip = zext i8 %numskipbits to i32
%shifted = lshr i32 %val, %skip
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%highbitscleared = shl i32 %shifted, %sh_prom
%masked = lshr i32 %highbitscleared, %sh_prom
ret i32 %masked
}
define i32 @bextr32_d5_skipextrauses(i32 %val, i32 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr32_d5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: xorl %ecx, %ecx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shll %cl, %esi
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: movl %eax, (%esp)
; X86-NOBMI-NEXT: calll use32
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: addl $8, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr32_d5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: subl $8, %esp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: shll $8, %ecx
; X86-BMI1NOTBM-NEXT: movzbl %al, %edx
; X86-BMI1NOTBM-NEXT: orl %ecx, %edx
; X86-BMI1NOTBM-NEXT: bextrl %edx, {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %eax, (%esp)
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: calll use32
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: addl $8, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr32_d5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: subl $8, %esp
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1BMI2-NEXT: shrxl %ecx, {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %esi
; X86-BMI1BMI2-NEXT: movl %ecx, (%esp)
; X86-BMI1BMI2-NEXT: calll use32
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: addl $8, %esp
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr32_d5_skipextrauses:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: movl %edi, %ebx
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: shrl %cl, %ebx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %ebx
; X64-NOBMI-NEXT: shrl %cl, %ebx
; X64-NOBMI-NEXT: movl %esi, %edi
; X64-NOBMI-NEXT: callq use32
; X64-NOBMI-NEXT: movl %ebx, %eax
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr32_d5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbx
Experimental re-land of [X86][BMI1] X86DAGToDAGISel: select BEXTR from x << (32 - y) >> (32 - y) pattern This initially landed in rL345014, but was reverted in rL345017 due to sanitizer-x86_64-linux-fast buildbot failure in check-lld (ELF/relocatable-versioned.s) test. While i'm not yet quite sure what is the problem, one obvious thing here is that extra truncation roundtrip. Maybe that's it? If not, will re-revert. Differential Revision: https://reviews.llvm.org/D53521 llvm-svn: 345027
2018-10-23 21:19:31 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %ebx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movl %esi, %edi
; X64-BMI1NOTBM-NEXT: callq use32
; X64-BMI1NOTBM-NEXT: movl %ebx, %eax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr32_d5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: shrxl %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %ebx
; X64-BMI1BMI2-NEXT: movl %esi, %edi
; X64-BMI1BMI2-NEXT: callq use32
; X64-BMI1BMI2-NEXT: movl %ebx, %eax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i32 %val, %numskipbits
%numhighbits = sub i32 32, %numlowbits
%highbitscleared = shl i32 %shifted, %numhighbits
%masked = lshr i32 %highbitscleared, %numhighbits
call void @use32(i32 %numskipbits)
ret i32 %masked
}
; 64-bit.
define i64 @bextr64_d0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_d0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %edx, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB56_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB56_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shldl %cl, %edi, %eax
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB56_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB56_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %ebx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB56_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.5:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB56_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %ebx, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB56_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.7:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB56_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_d0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edx, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB56_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB56_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %eax
; X86-BMI1NOTBM-NEXT: shll %cl, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB56_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB56_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB56_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.5:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB56_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebx, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB56_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.7:
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB56_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_d0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB56_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB56_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shlxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB56_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: movl $0, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB56_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB56_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.5:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB56_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB56_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.7:
; X86-BMI1BMI2-NEXT: movl %edi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB56_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_d0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_d0:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_d0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%highbitscleared = shl i64 %shifted, %numhighbits
%masked = lshr i64 %highbitscleared, %numhighbits
ret i64 %masked
}
define i64 @bextr64_d1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_d1_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %edx, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB57_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB57_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shldl %cl, %edi, %eax
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB57_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB57_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %ebx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB57_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.5:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB57_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %ebx, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB57_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.7:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB57_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_d1_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edx, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB57_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB57_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %eax
; X86-BMI1NOTBM-NEXT: shll %cl, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB57_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB57_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB57_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.5:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB57_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebx, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB57_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.7:
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB57_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_d1_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %esi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB57_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB57_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shlxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB57_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: movl $0, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB57_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB57_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.5:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB57_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB57_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.7:
; X86-BMI1BMI2-NEXT: movl %edi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB57_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_d1_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_d1_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_d1_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: # kill: def $edx killed $edx def $rdx
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%highbitscleared = shl i64 %shifted, %sh_prom
%masked = lshr i64 %highbitscleared, %sh_prom
ret i64 %masked
}
define i64 @bextr64_d2_load(i64* %w, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_d2_load:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %edi
; X86-NOBMI-NEXT: movl 4(%eax), %edx
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %edx, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB58_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB58_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shldl %cl, %edi, %eax
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB58_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB58_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %ebx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB58_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.5:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB58_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %ebx, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB58_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.7:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB58_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_d2_load:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %edi
; X86-BMI1NOTBM-NEXT: movl 4(%eax), %edx
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edx, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB58_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB58_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %eax
; X86-BMI1NOTBM-NEXT: shll %cl, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB58_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB58_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB58_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.5:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB58_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebx, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB58_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.7:
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB58_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_d2_load:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl (%edx), %eax
; X86-BMI1BMI2-NEXT: movl 4(%edx), %edx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB58_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB58_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shlxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB58_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: movl $0, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB58_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB58_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.5:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB58_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB58_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.7:
; X86-BMI1BMI2-NEXT: movl %edi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB58_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_d2_load:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq (%rdi), %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rax
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_d2_load:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rdi), %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_d2_load:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%highbitscleared = shl i64 %shifted, %numhighbits
%masked = lshr i64 %highbitscleared, %numhighbits
ret i64 %masked
}
define i64 @bextr64_d3_load_indexzext(i64* %w, i8 %numskipbits, i8 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_d3_load_indexzext:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl (%eax), %edi
; X86-NOBMI-NEXT: movl 4(%eax), %edx
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %edx, %edi
; X86-NOBMI-NEXT: xorl %esi, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB59_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edi
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB59_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shldl %cl, %edi, %eax
; X86-NOBMI-NEXT: shll %cl, %edi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB59_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB59_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %ebx, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB59_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.5:
; X86-NOBMI-NEXT: movl %edi, %esi
; X86-NOBMI-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB59_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %ebx, %esi
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB59_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.7:
; X86-NOBMI-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB59_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_d3_load_indexzext:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl (%eax), %edi
; X86-BMI1NOTBM-NEXT: movl 4(%eax), %edx
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edx, %edi
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB59_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edi
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB59_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %edi, %eax
; X86-BMI1NOTBM-NEXT: shll %cl, %edi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl %edi, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB59_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %eax, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB59_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebx, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl $0, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB59_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.5:
; X86-BMI1NOTBM-NEXT: movl %edi, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB59_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebx, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB59_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.7:
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB59_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_d3_load_indexzext:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl (%edx), %eax
; X86-BMI1BMI2-NEXT: movl 4(%edx), %edx
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB59_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %esi, %eax
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB59_2:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %esi
; X86-BMI1BMI2-NEXT: shlxl %ecx, %eax, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB59_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
; X86-BMI1BMI2-NEXT: movl $0, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB59_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB59_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.5:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB59_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edi
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB59_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.7:
; X86-BMI1BMI2-NEXT: movl %edi, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB59_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_d3_load_indexzext:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: movq (%rdi), %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_d3_load_indexzext:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rdi), %rax
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_d3_load_indexzext:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: # kill: def $edx killed $edx def $rdx
; X64-BMI1BMI2-NEXT: # kill: def $esi killed $esi def $rsi
; X64-BMI1BMI2-NEXT: shrxq %rsi, (%rdi), %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: retq
%val = load i64, i64* %w
%skip = zext i8 %numskipbits to i64
%shifted = lshr i64 %val, %skip
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%highbitscleared = shl i64 %shifted, %sh_prom
%masked = lshr i64 %highbitscleared, %sh_prom
ret i64 %masked
}
define i64 @bextr64_d5_skipextrauses(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_d5_skipextrauses:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %ebp
; X86-NOBMI-NEXT: pushl %ebx
; X86-NOBMI-NEXT: pushl %edi
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: subl $12, %esp
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %edx, %esi
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: shrdl %cl, %edx, %ebx
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB60_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %esi, %ebx
; X86-NOBMI-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB60_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shldl %cl, %ebx, %esi
; X86-NOBMI-NEXT: shll %cl, %ebx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl %ebx, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB60_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %esi, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB60_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: movl %ebp, %esi
; X86-NOBMI-NEXT: shrl %cl, %esi
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl $0, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB60_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.5:
; X86-NOBMI-NEXT: movl %ebx, %edx
; X86-NOBMI-NEXT: movl %esi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB60_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %ebp, %edx
; X86-NOBMI-NEXT: testb $32, %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB60_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: # %bb.7:
; X86-NOBMI-NEXT: movl %edx, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB60_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-NOBMI-NEXT: subl $8, %esp
; X86-NOBMI-NEXT: pushl %ecx
; X86-NOBMI-NEXT: pushl %eax
; X86-NOBMI-NEXT: calll use64
; X86-NOBMI-NEXT: addl $16, %esp
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: movl %edi, %edx
; X86-NOBMI-NEXT: addl $12, %esp
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: popl %edi
; X86-NOBMI-NEXT: popl %ebx
; X86-NOBMI-NEXT: popl %ebp
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_d5_skipextrauses:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %ebp
; X86-BMI1NOTBM-NEXT: pushl %ebx
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: subl $12, %esp
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
; X86-BMI1NOTBM-NEXT: movl %eax, %ecx
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edx, %ebx
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB60_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %ebx
; X86-BMI1NOTBM-NEXT: xorl %esi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB60_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shldl %cl, %ebx, %esi
; X86-BMI1NOTBM-NEXT: shll %cl, %ebx
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl %ebx, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB60_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %esi, %ebp
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB60_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: movl %ebp, %esi
; X86-BMI1NOTBM-NEXT: shrl %cl, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl $0, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB60_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.5:
; X86-BMI1NOTBM-NEXT: movl %ebx, %edx
; X86-BMI1NOTBM-NEXT: movl %esi, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB60_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: shrdl %cl, %ebp, %edx
; X86-BMI1NOTBM-NEXT: testb $32, %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB60_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.7:
; X86-BMI1NOTBM-NEXT: movl %edx, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB60_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1NOTBM-NEXT: subl $8, %esp
; X86-BMI1NOTBM-NEXT: pushl %ecx
; X86-BMI1NOTBM-NEXT: pushl %eax
; X86-BMI1NOTBM-NEXT: calll use64
; X86-BMI1NOTBM-NEXT: addl $16, %esp
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: addl $12, %esp
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: popl %ebx
; X86-BMI1NOTBM-NEXT: popl %ebp
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_d5_skipextrauses:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %ebx
; X86-BMI1BMI2-NEXT: pushl %edi
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl %eax, %ecx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %edi
; X86-BMI1BMI2-NEXT: shrxl %eax, %edx, %edx
; X86-BMI1BMI2-NEXT: xorl %esi, %esi
; X86-BMI1BMI2-NEXT: testb $32, %al
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB60_2
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %edi
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB60_2:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shldl %cl, %edi, %edx
; X86-BMI1BMI2-NEXT: shlxl %ecx, %edi, %ebx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB60_4
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %ebx, %edx
; X86-BMI1BMI2-NEXT: movl $0, %ebx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB60_4:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB60_6
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.5:
; X86-BMI1BMI2-NEXT: movl %edi, %esi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB60_6:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %ebx
; X86-BMI1BMI2-NEXT: testb $32, %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: jne .LBB60_8
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: # %bb.7:
; X86-BMI1BMI2-NEXT: movl %ebx, %edi
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB60_8:
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X86-BMI1BMI2-NEXT: subl $8, %esp
; X86-BMI1BMI2-NEXT: pushl %ecx
; X86-BMI1BMI2-NEXT: pushl %eax
; X86-BMI1BMI2-NEXT: calll use64
; X86-BMI1BMI2-NEXT: addl $16, %esp
; X86-BMI1BMI2-NEXT: movl %edi, %eax
; X86-BMI1BMI2-NEXT: movl %esi, %edx
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: popl %edi
; X86-BMI1BMI2-NEXT: popl %ebx
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_d5_skipextrauses:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: pushq %rbx
; X64-NOBMI-NEXT: movq %rdi, %rbx
; X64-NOBMI-NEXT: movl %esi, %ecx
; X64-NOBMI-NEXT: shrq %cl, %rbx
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; X64-NOBMI-NEXT: negb %dl
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rbx
; X64-NOBMI-NEXT: shrq %cl, %rbx
; X64-NOBMI-NEXT: movq %rsi, %rdi
; X64-NOBMI-NEXT: callq use64
; X64-NOBMI-NEXT: movq %rbx, %rax
; X64-NOBMI-NEXT: popq %rbx
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_d5_skipextrauses:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: pushq %rbx
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X` Summary: As discussed in previous review, and noted in the FIXME, if `X` is actually an `lshr Y, Z` (logical!), we can fold the `Z` into 'control`, and let the `BEXTR` do this too. We could just insert those 8 bits of shift amount into control, but it is better to instead zero-extend them, and 'or' them in place. We can only do this for `lshr`, not `ashr`, because we do not know that the mask cover only the bits of `Y`, and not any of the sign-extended bits. The obvious question is, is this actually legal to do? I believe it is. Relevant quotes, from `Intel® 64 and IA-32 Architectures Software Developer’s Manual`, `BEXTR — Bit Field Extract`: * `Bit 7:0 of the second source operand specifies the starting bit position of bit extraction.` * `A START value exceeding the operand size will not extract any bits from the second source operand.` * `Only bit positions up to (OperandSize -1) of the first source operand are extracted.` * `All higher order bits in the destination operand (starting at bit position LENGTH) are zeroed.` * `The destination register is cleared if no bits are extracted.` FIXME: if we can do this, i wonder if we should prefer `BEXTR` over `BZHI` in such cases. Reviewers: RKSimon, craig.topper, spatel, andreadb Reviewed By: RKSimon, craig.topper, andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54095 llvm-svn: 347048
2018-11-16 21:04:54 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rbx
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; X64-BMI1NOTBM-NEXT: movq %rsi, %rdi
; X64-BMI1NOTBM-NEXT: callq use64
; X64-BMI1NOTBM-NEXT: movq %rbx, %rax
; X64-BMI1NOTBM-NEXT: popq %rbx
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_d5_skipextrauses:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: pushq %rbx
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rbx
; X64-BMI1BMI2-NEXT: movq %rsi, %rdi
; X64-BMI1BMI2-NEXT: callq use64
; X64-BMI1BMI2-NEXT: movq %rbx, %rax
; X64-BMI1BMI2-NEXT: popq %rbx
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%highbitscleared = shl i64 %shifted, %numhighbits
%masked = lshr i64 %highbitscleared, %numhighbits
call void @use64(i64 %numskipbits)
ret i64 %masked
}
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; 64-bit, but with 32-bit output
; Everything done in 64-bit, truncation happens last.
define i32 @bextr64_32_d0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_d0:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %esi, %edx
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB61_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %eax, %edx
; X86-NOBMI-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB61_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: movb $64, %cl
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shldl %cl, %edx, %eax
; X86-NOBMI-NEXT: shll %cl, %edx
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: je .LBB61_4
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.3:
; X86-NOBMI-NEXT: movl %edx, %eax
; X86-NOBMI-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB61_4:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: shrdl %cl, %eax, %edx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB61_6
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.5:
; X86-NOBMI-NEXT: movl %edx, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB61_6:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_d0:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl %esi, %eax
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB61_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %eax, %edx
; X86-BMI1NOTBM-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB61_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: movb $64, %cl
; X86-BMI1NOTBM-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: shldl %cl, %edx, %eax
; X86-BMI1NOTBM-NEXT: shll %cl, %edx
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: je .LBB61_4
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.3:
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB61_4:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: shrdl %cl, %eax, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %eax
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB61_6
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.5:
; X86-BMI1NOTBM-NEXT: movl %edx, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB61_6:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_d0:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB61_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: movl %edx, %eax
; X86-BMI1BMI2-NEXT: xorl %edx, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB61_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: movb $64, %cl
; X86-BMI1BMI2-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: shldl %cl, %eax, %edx
; X86-BMI1BMI2-NEXT: shlxl %ecx, %eax, %eax
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB61_4
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.3:
; X86-BMI1BMI2-NEXT: movl %eax, %edx
; X86-BMI1BMI2-NEXT: xorl %eax, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB61_4:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: shrdl %cl, %edx, %eax
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB61_6
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.5:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %edx, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB61_6:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_d0:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shlq %cl, %rax
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_d0:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_d0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhiq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits
%highbitscleared = shl i64 %shifted, %numhighbits
%masked = lshr i64 %highbitscleared, %numhighbits
%res = trunc i64 %masked to i32
ret i32 %res
}
; Shifting happens in 64-bit, then truncation. Masking is 32-bit.
define i32 @bextr64_32_d1(i64 %val, i64 %numskipbits, i32 %numlowbits) nounwind {
; X86-NOBMI-LABEL: bextr64_32_d1:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: pushl %esi
; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOBMI-NEXT: movl %esi, %eax
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: shrdl %cl, %esi, %edx
; X86-NOBMI-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: jne .LBB62_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: # %bb.1:
; X86-NOBMI-NEXT: movl %edx, %eax
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-NOBMI-NEXT: .LBB62_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-NOBMI-NEXT: xorl %ecx, %ecx
; X86-NOBMI-NEXT: subb {{[0-9]+}}(%esp), %cl
; X86-NOBMI-NEXT: shll %cl, %eax
; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
; X86-NOBMI-NEXT: shrl %cl, %eax
; X86-NOBMI-NEXT: popl %esi
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: bextr64_32_d1:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: pushl %edi
; X86-BMI1NOTBM-NEXT: pushl %esi
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1NOTBM-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BMI1NOTBM-NEXT: movl %edi, %edx
; X86-BMI1NOTBM-NEXT: shrl %cl, %edx
; X86-BMI1NOTBM-NEXT: shrdl %cl, %edi, %esi
; X86-BMI1NOTBM-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: jne .LBB62_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: # %bb.1:
; X86-BMI1NOTBM-NEXT: movl %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1NOTBM-NEXT: .LBB62_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1NOTBM-NEXT: shll $8, %eax
; X86-BMI1NOTBM-NEXT: bextrl %eax, %edx, %eax
; X86-BMI1NOTBM-NEXT: popl %esi
; X86-BMI1NOTBM-NEXT: popl %edi
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1BMI2-LABEL: bextr64_32_d1:
; X86-BMI1BMI2: # %bb.0:
; X86-BMI1BMI2-NEXT: pushl %esi
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-BMI1BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-BMI1BMI2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BMI1BMI2-NEXT: shrdl %cl, %esi, %edx
; X86-BMI1BMI2-NEXT: testb $32, %cl
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: je .LBB62_2
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: # %bb.1:
; X86-BMI1BMI2-NEXT: shrxl %ecx, %esi, %edx
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation llvm-svn: 362364
2019-06-03 16:44:09 +08:00
; X86-BMI1BMI2-NEXT: .LBB62_2:
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X86-BMI1BMI2-NEXT: bzhil %eax, %edx, %eax
; X86-BMI1BMI2-NEXT: popl %esi
; X86-BMI1BMI2-NEXT: retl
;
; X64-NOBMI-LABEL: bextr64_32_d1:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rsi, %rcx
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI-NEXT: shrq %cl, %rax
; X64-NOBMI-NEXT: negb %dl
; X64-NOBMI-NEXT: movl %edx, %ecx
; X64-NOBMI-NEXT: shll %cl, %eax
; X64-NOBMI-NEXT: shrl %cl, %eax
; X64-NOBMI-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: bextr64_32_d1:
; X64-BMI1NOTBM: # %bb.0:
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: shll $8, %edx
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
[X86] X86DAGToDAGISel::matchBitExtract(): prepare 'control' in 32 bits Summary: Noticed while looking at D56052. ``` // The 'control' of BEXTR has the pattern of: // [15...8 bit][ 7...0 bit] location // [ bit count][ shift] name // I.e. 0b000000011'00000001 means (x >> 0b1) & 0b11 ``` I.e. we do not care about any of the bits aside from the low 16 bits. So there is no point in doing the `slh`,`or` in 64 bits, let's just do everything in 32 bits, and anyext if needed. We could do that in 16 even, but we intentionally don't zext to i16 (longer encoding IIRC), so i'm guessing the same applies here. Reviewers: craig.topper, andreadb, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D56715 llvm-svn: 353073
2019-02-05 03:04:26 +08:00
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
X86DAGToDAGISel::matchBitExtract() with truncation (PR36419) Summary: Previously in D54095 i have added support for extraction of `lshr` from `X` if we are to produce `BEXTR`. That was good, but the fix was partial, there was still [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]]. That pattern can also appear, roughly, when you have a large (64-bit) storage, and the consume bits from it. It will not be unexpected if you will be doing further computations in 32-bit width. And then the current code breaks, as the tests show. The basic idea/pattern here is following: 1. We have `i64` input 2. We perform `i64` right-shift on it. 3. We `trunc`ate that shifted value 4. We do all further work (masking) in `i32` Since we see `trunc`ation and not `lshr`, we give up, and stop trying to extract that right-shift. BUT. The mask is `i32`, therefore we can extend both of the operands of the masking (`and`) to `i64` and truncate the result after masking: https://rise4fun.com/Alive/K4B ``` Name: @bextr64_32_b1 -> @bextr64_32_b0 %shiftedval = lshr i64 %val, %numskipbits %truncshiftedval = trunc i64 %shiftedval to i32 %widenumlowbits1 = zext i8 %numlowbits to i32 %notmask1 = shl nsw i32 -1, %widenumlowbits1 %mask1 = xor i32 %notmask1, -1 %res = and i32 %truncshiftedval, %mask1 => %shiftedval = lshr i64 %val, %numskipbits %widenumlowbits = zext i8 %numlowbits to i64 %notmask = shl nsw i64 -1, %widenumlowbits %mask = xor i64 %notmask, -1 %wideres = and i64 %shiftedval, %mask %res = trunc i64 %wideres to i32 ``` Thus, we are again able to extract that `lshr` into `BEXTR`'s control. Now, the perf (via `llvm-exegesis`) of the snippet suggests that it is not a good idea: ``` $ cat /tmp/old.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RSI # LLVM-EXEGESIS-LIVEIN EDX # LLVM-EXEGESIS-LIVEIN RDI movq %rsi, %rcx shrq %cl, %rdi shll $8, %edx bextrl %edx, %edi, %eax $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-1e0082.o --- mode: latency key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.6638, per_snippet_value: 2.6552 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... $ cat /tmp/old.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-43e346.o --- mode: uops key: instructions: - 'MOV64rr RCX RSI' - 'SHR64rCL RDI RDI' - 'SHL32ri EDX EDX i_0x8' - 'BEXTR32rr EAX EDI EDX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 4889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C74889F148D3EFC1E208C4E268F7C7C3 ... ``` vs ``` $ cat /tmp/new.s # bextr64_32_b1 # LLVM-EXEGESIS-LIVEIN RDX # LLVM-EXEGESIS-LIVEIN SIL # LLVM-EXEGESIS-LIVEIN RDI shlq $8, %rdx movzbl %sil, %eax orq %rdx, %rax bextrq %rax, %rdi, %rax $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=latency -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-8944f1.o --- mode: latency key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: latency, value: 0.7454, per_snippet_value: 2.9816 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... $ cat /tmp/new.s | ./bin/llvm-exegesis -mode=uops -snippets-file=- Check generated assembly with: /usr/bin/objdump -d /tmp/snippet-da403c.o --- mode: uops key: instructions: - 'SHL64ri RDX RDX i_0x8' - 'MOVZX32rr8 EAX SIL' - 'OR64rr RAX RAX RDX' - 'BEXTR64rr RAX RDI RAX' config: '' register_initial_values: [] cpu_name: bdver2 llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: PdFPU0, value: 0, per_snippet_value: 0 } - { key: PdFPU1, value: 0, per_snippet_value: 0 } - { key: PdFPU2, value: 0, per_snippet_value: 0 } - { key: PdFPU3, value: 0, per_snippet_value: 0 } - { key: NumMicroOps, value: 1.2571, per_snippet_value: 5.0284 } error: '' info: '' assembled_snippet: 48C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C748C1E208400FB6C64809D0C4E2F8F7C7C3 ... ``` ^ latency increased (worse). Except //maybe// not really. Like with all synthetic benchmarks, they //may// be misleading. Let's take a look on some actual real-world hotpath. In this case it's 'my' [[ https://github.com/darktable-org/rawspeed | RawSpeed ]]'s `BitStream<>::peekBitsNoFill()`, in [[ https://github.com/darktable-org/rawspeed/blob/e3316dc85127c2c29baa40f998f198a7b278bf36/src/librawspeed/decompressors/VC5Decompressor.cpp#L814 | GoPro VC5 decompressor ]]: ``` raw.pixls.us-unique/GoPro/HERO6 Black$ /usr/src/googlebenchmark/tools/compare.py -a benchmarks ~/rawspeed/build-clangs1-{old,new}/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR RUNNING: /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmplwbKEM 2018-12-22 21:23:03 Running /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench Run on (8 X 4012.81 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.41, 2.41, 2.03 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 40 ms 40 ms 128 0.322244 7.96974 12M 37.4457M 298.534M 3.12047 24.8778 0.040465 GOPR9172.GPR/threads:8/real_time_median 39 ms 39 ms 128 0.312606 7.99155 12M 38.387M 306.788M 3.19891 25.5656 0.039115 GOPR9172.GPR/threads:8/real_time_stddev 4 ms 3 ms 128 0.0271557 0.130575 0 2.4941M 21.3909M 0.207842 1.78257 3.81081m RUNNING: /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench --benchmark_counters_tabular=true --benchmark_min_time=0.00000001 --benchmark_repetitions=128 GOPR9172.GPR --benchmark_display_aggregates_only=true --benchmark_out=/tmp/tmpWAkan9 2018-12-22 21:23:08 Running /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Run on (8 X 4013.1 MHz CPU s) CPU Caches: L1 Data 16K (x8) L1 Instruction 64K (x4) L2 Unified 2048K (x4) L3 Unified 8192K (x1) Load Average: 3.78, 2.50, 2.06 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Benchmark Time CPU Iterations CPUTime,s CPUTime/WallTime Pixels Pixels/CPUTime Pixels/WallTime Raws/CPUTime Raws/WallTime WallTime,s ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_mean 39 ms 39 ms 128 0.311533 7.97323 12M 38.6828M 308.471M 3.22356 25.706 0.0390928 GOPR9172.GPR/threads:8/real_time_median 38 ms 38 ms 128 0.304231 7.99005 12M 39.4437M 315.527M 3.28698 26.294 0.0380316 GOPR9172.GPR/threads:8/real_time_stddev 3 ms 3 ms 128 0.0229149 0.133814 0 2.26225M 19.1421M 0.188521 1.59517 3.13671m Comparing /home/lebedevri/rawspeed/build-clangs1-old/src/utilities/rsbench/rsbench to /home/lebedevri/rawspeed/build-clangs1-new/src/utilities/rsbench/rsbench Benchmark Time CPU Time Old Time New CPU Old CPU New -------------------------------------------------------------------------------------------------------------------------------------- GOPR9172.GPR/threads:8/real_time_pvalue 0.0000 0.0000 U Test, Repetitions: 128 vs 128 GOPR9172.GPR/threads:8/real_time_mean -0.0339 -0.0316 40 39 40 39 GOPR9172.GPR/threads:8/real_time_median -0.0277 -0.0274 39 38 39 38 GOPR9172.GPR/threads:8/real_time_stddev -0.1769 -0.1267 4 3 3 3 ``` I.e. this results in //roughly// -3% improvements in perf. While this will help [[ https://bugs.llvm.org/show_bug.cgi?id=36419 | PR36419 ]], it won't address it fully. Reviewers: RKSimon, craig.topper, andreadb, spatel Reviewed By: craig.topper Subscribers: courbet, llvm-commits Differential Revision: https://reviews.llvm.org/D56052 llvm-svn: 351253
2019-01-16 05:31:18 +08:00
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419) llvm-svn: 350000
2018-12-22 18:38:05 +08:00
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_d1:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%truncshifted = trunc i64 %shifted to i32
%numhighbits = sub i32 32, %numlowbits
%highbitscleared = shl i32 %truncshifted, %numhighbits
%masked = lshr i32 %highbitscleared, %numhighbits
ret i32 %masked
}
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
; ---------------------------------------------------------------------------- ;
; Constant
; ---------------------------------------------------------------------------- ;
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
2018-09-24 21:24:20 +08:00
; https://bugs.llvm.org/show_bug.cgi?id=38938
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @pr38938(i32* %a0, i64* %a1) nounwind {
[X86] Restore X86ISelDAGToDAG::matchBEXTRFromAnd. Teach address matching to create a BEXTR pattern from a (shl (and X, mask >> C1) if C1 can be folded into addressing mode. This is an alternative to D53080 since I think using a BEXTR for a shifted mask is definitely an improvement when the shl can be absorbed into addressing mode. The other cases I'm less sure about. We already have several tricks for handling an and of a shift in address matching. This adds a new case for BEXTR. I've moved the BEXTR matching code back to X86ISelDAGToDAG to allow it to match. I suppose alternatively we could directly emit a X86ISD::BEXTR node that isel could pattern match. But I'm trying to view BEXTR matching as an isel concern so DAG combine can see 'and' and 'shift' operations that are well understood. We did lose a couple cases from tbm_patterns.ll, but I think there are ways to recover that. I've also put back the manual load folding code in matchBEXTRFromAnd that I removed a few months ago in r324939. This gives us some more freedom to make decisions based on the ability to fold a load. I haven't done anything with that yet. Differential Revision: https://reviews.llvm.org/D53126 llvm-svn: 344270
2018-10-12 02:06:07 +08:00
; X86-NOBMI-LABEL: pr38938:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOBMI-NEXT: movl (%ecx), %ecx
; X86-NOBMI-NEXT: shrl $19, %ecx
; X86-NOBMI-NEXT: andl $4092, %ecx # imm = 0xFFC
; X86-NOBMI-NEXT: incl (%eax,%ecx)
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: pr38938:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: movl $2581, %edx # imm = 0xA15
; X86-BMI1NOTBM-NEXT: bextrl %edx, (%ecx), %ecx
; X86-BMI1NOTBM-NEXT: incl (%eax,%ecx,4)
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: pr38938:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1TBM-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1TBM-NEXT: bextrl $2581, (%ecx), %ecx # imm = 0xA15
; X86-BMI1TBM-NEXT: incl (%eax,%ecx,4)
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: pr38938:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBMBMI2-NEXT: movl $2581, %edx # imm = 0xA15
; X86-BMI1NOTBMBMI2-NEXT: bextrl %edx, (%ecx), %ecx
; X86-BMI1NOTBMBMI2-NEXT: incl (%eax,%ecx,4)
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: pr38938:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq (%rsi), %rax
; X64-NOBMI-NEXT: shrq $19, %rax
; X64-NOBMI-NEXT: andl $4092, %eax # imm = 0xFFC
; X64-NOBMI-NEXT: incl (%rdi,%rax)
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: pr38938:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $2581, %eax # imm = 0xA15
; X64-BMI1NOTBM-NEXT: bextrq %rax, (%rsi), %rax
; X64-BMI1NOTBM-NEXT: incl (%rdi,%rax,4)
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: pr38938:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrq $2581, (%rsi), %rax # imm = 0xA15
; X64-BMI1TBM-NEXT: incl (%rdi,%rax,4)
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: pr38938:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $2581, %eax # imm = 0xA15
; X64-BMI1NOTBMBMI2-NEXT: bextrq %rax, (%rsi), %rax
; X64-BMI1NOTBMBMI2-NEXT: incl (%rdi,%rax,4)
; X64-BMI1NOTBMBMI2-NEXT: retq
[NFC][x86][AArch64] Add BEXTR-like test patterns. Summary: Also, adjust the check prefixes so that we actually get to check the BMI1-only-case. Reviewers: craig.topper, RKSimon, spatel, javed.absar Reviewed By: RKSimon Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48490 llvm-svn: 342623
2018-09-20 15:54:49 +08:00
%tmp = load i64, i64* %a1, align 8
%tmp1 = lshr i64 %tmp, 21
%tmp2 = and i64 %tmp1, 1023
%tmp3 = getelementptr inbounds i32, i32* %a0, i64 %tmp2
%tmp4 = load i32, i32* %tmp3, align 4
%tmp5 = add nsw i32 %tmp4, 1
store i32 %tmp5, i32* %tmp3, align 4
ret void
}
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
2018-09-24 21:24:20 +08:00
; The most canonical variant
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @c0_i32(i32 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
2018-09-24 21:24:20 +08:00
; X86-NOBMI-LABEL: c0_i32:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: shrl $19, %eax
; X86-NOBMI-NEXT: andl $1023, %eax # imm = 0x3FF
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: c0_i32:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl $2579, %eax # imm = 0xA13
; X86-BMI1NOTBM-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: c0_i32:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: bextrl $2579, {{[0-9]+}}(%esp), %eax # imm = 0xA13
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: c0_i32:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl $2579, %eax # imm = 0xA13
; X86-BMI1NOTBMBMI2-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: c0_i32:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movl %edi, %eax
; X64-NOBMI-NEXT: shrl $19, %eax
; X64-NOBMI-NEXT: andl $1023, %eax # imm = 0x3FF
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: c0_i32:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $2579, %eax # imm = 0xA13
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: c0_i32:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrl $2579, %edi, %eax # imm = 0xA13
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: c0_i32:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $2579, %eax # imm = 0xA13
; X64-BMI1NOTBMBMI2-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBMBMI2-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 1023
ret i32 %tmp1
}
; Should be still fine, but the mask is shifted
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @c1_i32(i32 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
2018-09-24 21:24:20 +08:00
; X86-LABEL: c1_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $19, %eax
; X86-NEXT: andl $4092, %eax # imm = 0xFFC
; X86-NEXT: retl
;
; X64-LABEL: c1_i32:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shrl $19, %eax
; X64-NEXT: andl $4092, %eax # imm = 0xFFC
; X64-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 4092
ret i32 %tmp1
}
; Should be still fine, but the result is shifted left afterwards
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @c2_i32(i32 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
2018-09-24 21:24:20 +08:00
; X86-LABEL: c2_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $17, %eax
; X86-NEXT: andl $4092, %eax # imm = 0xFFC
; X86-NEXT: retl
;
; X64-LABEL: c2_i32:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shrl $17, %eax
; X64-NEXT: andl $4092, %eax # imm = 0xFFC
; X64-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 1023
%tmp2 = shl i32 %tmp1, 2
ret i32 %tmp2
}
; The mask covers newly shifted-in bit
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i32 @c4_i32_bad(i32 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants It would be best to introduce ISD::BitFieldExtract, because clearly more than one backend faces the same problem. But for now let's solve this in the x86-specific DAG combine. https://bugs.llvm.org/show_bug.cgi?id=38938 llvm-svn: 342880
2018-09-24 21:24:20 +08:00
; X86-LABEL: c4_i32_bad:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $19, %eax
; X86-NEXT: andl $-2, %eax
; X86-NEXT: retl
;
; X64-LABEL: c4_i32_bad:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: shrl $19, %eax
; X64-NEXT: andl $-2, %eax
; X64-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 16382
ret i32 %tmp1
}
[NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests llvm-svn: 343404
2018-09-30 20:42:08 +08:00
; i64
; The most canonical variant
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i64 @c0_i64(i64 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests llvm-svn: 343404
2018-09-30 20:42:08 +08:00
; X86-NOBMI-LABEL: c0_i64:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: shrl $19, %eax
; X86-NOBMI-NEXT: andl $1023, %eax # imm = 0x3FF
; X86-NOBMI-NEXT: xorl %edx, %edx
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: c0_i64:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl $2579, %eax # imm = 0xA13
; X86-BMI1NOTBM-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: xorl %edx, %edx
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: c0_i64:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: bextrl $2579, {{[0-9]+}}(%esp), %eax # imm = 0xA13
; X86-BMI1TBM-NEXT: xorl %edx, %edx
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: c0_i64:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl $2579, %eax # imm = 0xA13
; X86-BMI1NOTBMBMI2-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: xorl %edx, %edx
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: c0_i64:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: movq %rdi, %rax
; X64-NOBMI-NEXT: shrq $51, %rax
; X64-NOBMI-NEXT: andl $1023, %eax # imm = 0x3FF
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: c0_i64:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $2611, %eax # imm = 0xA33
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: c0_i64:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrq $2611, %rdi, %rax # imm = 0xA33
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: c0_i64:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $2611, %eax # imm = 0xA33
; X64-BMI1NOTBMBMI2-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBMBMI2-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 1023
ret i64 %tmp1
}
; Should be still fine, but the mask is shifted
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i64 @c1_i64(i64 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests llvm-svn: 343404
2018-09-30 20:42:08 +08:00
; X86-LABEL: c1_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $19, %eax
; X86-NEXT: andl $4092, %eax # imm = 0xFFC
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LABEL: c1_i64:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shrq $51, %rax
; X64-NEXT: andl $4092, %eax # imm = 0xFFC
; X64-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 4092
ret i64 %tmp1
}
; Should be still fine, but the result is shifted left afterwards
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i64 @c2_i64(i64 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests llvm-svn: 343404
2018-09-30 20:42:08 +08:00
; X86-LABEL: c2_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $17, %eax
; X86-NEXT: andl $4092, %eax # imm = 0xFFC
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LABEL: c2_i64:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shrq $49, %rax
; X64-NEXT: andl $4092, %eax # imm = 0xFFC
; X64-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 1023
%tmp2 = shl i64 %tmp1, 2
ret i64 %tmp2
}
; The mask covers newly shifted-in bit
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define i64 @c4_i64_bad(i64 %arg) nounwind {
[NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests llvm-svn: 343404
2018-09-30 20:42:08 +08:00
; X86-LABEL: c4_i64_bad:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $19, %eax
; X86-NEXT: andl $-2, %eax
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LABEL: c4_i64_bad:
; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shrq $51, %rax
; X64-NEXT: andl $-2, %eax
; X64-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 16382
ret i64 %tmp1
}
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; ---------------------------------------------------------------------------- ;
; Constant, storing the result afterwards.
; ---------------------------------------------------------------------------- ;
; i32
; The most canonical variant
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @c5_i32(i32 %arg, i32* %ptr) nounwind {
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; X86-NOBMI-LABEL: c5_i32:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOBMI-NEXT: shrl $19, %ecx
; X86-NOBMI-NEXT: andl $1023, %ecx # imm = 0x3FF
; X86-NOBMI-NEXT: movl %ecx, (%eax)
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: c5_i32:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl $2579, %ecx # imm = 0xA13
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: c5_i32:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1TBM-NEXT: bextrl $2579, {{[0-9]+}}(%esp), %ecx # imm = 0xA13
; X86-BMI1TBM-NEXT: movl %ecx, (%eax)
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: c5_i32:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: movl $2579, %ecx # imm = 0xA13
; X86-BMI1NOTBMBMI2-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBMBMI2-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: c5_i32:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: shrl $19, %edi
; X64-NOBMI-NEXT: andl $1023, %edi # imm = 0x3FF
; X64-NOBMI-NEXT: movl %edi, (%rsi)
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: c5_i32:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $2579, %eax # imm = 0xA13
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBM-NEXT: movl %eax, (%rsi)
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: c5_i32:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrl $2579, %edi, %eax # imm = 0xA13
; X64-BMI1TBM-NEXT: movl %eax, (%rsi)
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: c5_i32:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $2579, %eax # imm = 0xA13
; X64-BMI1NOTBMBMI2-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBMBMI2-NEXT: movl %eax, (%rsi)
; X64-BMI1NOTBMBMI2-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 1023
store i32 %tmp1, i32* %ptr
ret void
}
; Should be still fine, but the mask is shifted
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @c6_i32(i32 %arg, i32* %ptr) nounwind {
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; X86-NOBMI-LABEL: c6_i32:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOBMI-NEXT: shrl $19, %ecx
; X86-NOBMI-NEXT: andl $4095, %ecx # imm = 0xFFF
; X86-NOBMI-NEXT: movl %ecx, (%eax)
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: c6_i32:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl $3091, %ecx # imm = 0xC13
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: c6_i32:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1TBM-NEXT: bextrl $3091, {{[0-9]+}}(%esp), %ecx # imm = 0xC13
; X86-BMI1TBM-NEXT: movl %ecx, (%eax)
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: c6_i32:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: movl $3091, %ecx # imm = 0xC13
; X86-BMI1NOTBMBMI2-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBMBMI2-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: c6_i32:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: shrl $19, %edi
; X64-NOBMI-NEXT: andl $4095, %edi # imm = 0xFFF
; X64-NOBMI-NEXT: movl %edi, (%rsi)
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: c6_i32:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $3091, %eax # imm = 0xC13
; X64-BMI1NOTBM-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBM-NEXT: movl %eax, (%rsi)
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: c6_i32:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrl $3091, %edi, %eax # imm = 0xC13
; X64-BMI1TBM-NEXT: movl %eax, (%rsi)
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: c6_i32:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $3091, %eax # imm = 0xC13
; X64-BMI1NOTBMBMI2-NEXT: bextrl %eax, %edi, %eax
; X64-BMI1NOTBMBMI2-NEXT: movl %eax, (%rsi)
; X64-BMI1NOTBMBMI2-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 4095
store i32 %tmp1, i32* %ptr
ret void
}
; Should be still fine, but the result is shifted left afterwards
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @c7_i32(i32 %arg, i32* %ptr) nounwind {
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; X86-LABEL: c7_i32:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shrl $17, %ecx
; X86-NEXT: andl $4092, %ecx # imm = 0xFFC
; X86-NEXT: movl %ecx, (%eax)
; X86-NEXT: retl
;
; X64-LABEL: c7_i32:
; X64: # %bb.0:
; X64-NEXT: shrl $17, %edi
; X64-NEXT: andl $4092, %edi # imm = 0xFFC
; X64-NEXT: movl %edi, (%rsi)
; X64-NEXT: retq
%tmp0 = lshr i32 %arg, 19
%tmp1 = and i32 %tmp0, 1023
%tmp2 = shl i32 %tmp1, 2
store i32 %tmp2, i32* %ptr
ret void
}
; i64
; The most canonical variant
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @c5_i64(i64 %arg, i64* %ptr) nounwind {
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; X86-NOBMI-LABEL: c5_i64:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOBMI-NEXT: shrl $19, %ecx
; X86-NOBMI-NEXT: andl $1023, %ecx # imm = 0x3FF
; X86-NOBMI-NEXT: movl %ecx, (%eax)
; X86-NOBMI-NEXT: movl $0, 4(%eax)
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: c5_i64:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl $2579, %ecx # imm = 0xA13
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBM-NEXT: movl $0, 4(%eax)
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: c5_i64:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1TBM-NEXT: bextrl $2579, {{[0-9]+}}(%esp), %ecx # imm = 0xA13
; X86-BMI1TBM-NEXT: movl %ecx, (%eax)
; X86-BMI1TBM-NEXT: movl $0, 4(%eax)
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: c5_i64:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: movl $2579, %ecx # imm = 0xA13
; X86-BMI1NOTBMBMI2-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBMBMI2-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBMBMI2-NEXT: movl $0, 4(%eax)
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: c5_i64:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: shrq $51, %rdi
; X64-NOBMI-NEXT: andl $1023, %edi # imm = 0x3FF
; X64-NOBMI-NEXT: movq %rdi, (%rsi)
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: c5_i64:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $2611, %eax # imm = 0xA33
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: movq %rax, (%rsi)
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: c5_i64:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrq $2611, %rdi, %rax # imm = 0xA33
; X64-BMI1TBM-NEXT: movq %rax, (%rsi)
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: c5_i64:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $2611, %eax # imm = 0xA33
; X64-BMI1NOTBMBMI2-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBMBMI2-NEXT: movq %rax, (%rsi)
; X64-BMI1NOTBMBMI2-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 1023
store i64 %tmp1, i64* %ptr
ret void
}
; Should be still fine, but the mask is shifted
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @c6_i64(i64 %arg, i64* %ptr) nounwind {
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; X86-NOBMI-LABEL: c6_i64:
; X86-NOBMI: # %bb.0:
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NOBMI-NEXT: shrl $19, %ecx
; X86-NOBMI-NEXT: andl $4095, %ecx # imm = 0xFFF
; X86-NOBMI-NEXT: movl %ecx, (%eax)
; X86-NOBMI-NEXT: movl $0, 4(%eax)
; X86-NOBMI-NEXT: retl
;
; X86-BMI1NOTBM-LABEL: c6_i64:
; X86-BMI1NOTBM: # %bb.0:
; X86-BMI1NOTBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBM-NEXT: movl $3091, %ecx # imm = 0xC13
; X86-BMI1NOTBM-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBM-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBM-NEXT: movl $0, 4(%eax)
; X86-BMI1NOTBM-NEXT: retl
;
; X86-BMI1TBM-LABEL: c6_i64:
; X86-BMI1TBM: # %bb.0:
; X86-BMI1TBM-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1TBM-NEXT: bextrl $3091, {{[0-9]+}}(%esp), %ecx # imm = 0xC13
; X86-BMI1TBM-NEXT: movl %ecx, (%eax)
; X86-BMI1TBM-NEXT: movl $0, 4(%eax)
; X86-BMI1TBM-NEXT: retl
;
; X86-BMI1NOTBMBMI2-LABEL: c6_i64:
; X86-BMI1NOTBMBMI2: # %bb.0:
; X86-BMI1NOTBMBMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI1NOTBMBMI2-NEXT: movl $3091, %ecx # imm = 0xC13
; X86-BMI1NOTBMBMI2-NEXT: bextrl %ecx, {{[0-9]+}}(%esp), %ecx
; X86-BMI1NOTBMBMI2-NEXT: movl %ecx, (%eax)
; X86-BMI1NOTBMBMI2-NEXT: movl $0, 4(%eax)
; X86-BMI1NOTBMBMI2-NEXT: retl
;
; X64-NOBMI-LABEL: c6_i64:
; X64-NOBMI: # %bb.0:
; X64-NOBMI-NEXT: shrq $51, %rdi
; X64-NOBMI-NEXT: andl $4095, %edi # imm = 0xFFF
; X64-NOBMI-NEXT: movq %rdi, (%rsi)
; X64-NOBMI-NEXT: retq
;
; X64-BMI1NOTBM-LABEL: c6_i64:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movl $3123, %eax # imm = 0xC33
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: movq %rax, (%rsi)
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1TBM-LABEL: c6_i64:
; X64-BMI1TBM: # %bb.0:
; X64-BMI1TBM-NEXT: bextrq $3123, %rdi, %rax # imm = 0xC33
; X64-BMI1TBM-NEXT: movq %rax, (%rsi)
; X64-BMI1TBM-NEXT: retq
;
; X64-BMI1NOTBMBMI2-LABEL: c6_i64:
; X64-BMI1NOTBMBMI2: # %bb.0:
; X64-BMI1NOTBMBMI2-NEXT: movl $3123, %eax # imm = 0xC33
; X64-BMI1NOTBMBMI2-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBMBMI2-NEXT: movq %rax, (%rsi)
; X64-BMI1NOTBMBMI2-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 4095
store i64 %tmp1, i64* %ptr
ret void
}
; Should be still fine, but the result is shifted left afterwards
[NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise Forgot about that. llvm-svn: 349999
2018-12-22 17:58:13 +08:00
define void @c7_i64(i64 %arg, i64* %ptr) nounwind {
[NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. As noted in https://reviews.llvm.org/D53080#inline-467678, this *may* get pessimized by that diff. llvm-svn: 344182
2018-10-11 04:50:52 +08:00
; X86-LABEL: c7_i64:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shrl $17, %ecx
; X86-NEXT: andl $4092, %ecx # imm = 0xFFC
; X86-NEXT: movl %ecx, (%eax)
; X86-NEXT: movl $0, 4(%eax)
; X86-NEXT: retl
;
; X64-LABEL: c7_i64:
; X64: # %bb.0:
; X64-NEXT: shrq $49, %rdi
; X64-NEXT: andl $4092, %edi # imm = 0xFFC
; X64-NEXT: movq %rdi, (%rsi)
; X64-NEXT: retq
%tmp0 = lshr i64 %arg, 51
%tmp1 = and i64 %tmp0, 1023
%tmp2 = shl i64 %tmp1, 2
store i64 %tmp2, i64* %ptr
ret void
}