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llvm-project/llvm/test/CodeGen/PowerPC/dyn-alloca-aligned.ll

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PPC: Support dynamic allocas with large alignment Support for dynamic stack alignments in the PPC backend has been unfinished, in part because it depends on dynamic stack realignment (which I only just recently implemented fully). Now we can also support dynamic allocas with higher than the default target stack alignment (16 bytes). In order to round-up the requested size to the maximum requested alignment, we need an additional register to hold the rounded-up size. We're already using one scavenged register to hold the previous stack-pointer value (which needs to be stored with the signal-safe stdux update), and so when we have dynamic allocas and a large alignment, we allocate two emergency spill slots for the scavenger. llvm-svn: 186562
2013-07-18 12:28:21 +08:00
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
%struct.s = type { i32, i32 }
declare void @bar(i32*, i32*) #0
define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 {
entry:
%0 = zext i32 %n to i64
%vla = alloca i32, i64 %0, align 128
%vla1 = alloca i32, i64 %0, align 128
%a2 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
TBAA: remove !tbaa from testing cases when they are not needed. llvm-svn: 191689
2013-10-01 02:17:35 +08:00
%1 = load i32* %a2, align 4
store i32 %1, i32* %vla1, align 128
PPC: Support dynamic allocas with large alignment Support for dynamic stack alignments in the PPC backend has been unfinished, in part because it depends on dynamic stack realignment (which I only just recently implemented fully). Now we can also support dynamic allocas with higher than the default target stack alignment (16 bytes). In order to round-up the requested size to the maximum requested alignment, we need an additional register to hold the rounded-up size. We're already using one scavenged register to hold the previous stack-pointer value (which needs to be stored with the signal-safe stdux update), and so when we have dynamic allocas and a large alignment, we allocate two emergency spill slots for the scavenger. llvm-svn: 186562
2013-07-18 12:28:21 +08:00
%b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
TBAA: remove !tbaa from testing cases when they are not needed. llvm-svn: 191689
2013-10-01 02:17:35 +08:00
%2 = load i32* %b, align 4
PPC: Support dynamic allocas with large alignment Support for dynamic stack alignments in the PPC backend has been unfinished, in part because it depends on dynamic stack realignment (which I only just recently implemented fully). Now we can also support dynamic allocas with higher than the default target stack alignment (16 bytes). In order to round-up the requested size to the maximum requested alignment, we need an additional register to hold the rounded-up size. We're already using one scavenged register to hold the previous stack-pointer value (which needs to be stored with the signal-safe stdux update), and so when we have dynamic allocas and a large alignment, we allocate two emergency spill slots for the scavenger. llvm-svn: 186562
2013-07-18 12:28:21 +08:00
%arrayidx3 = getelementptr inbounds i32* %vla1, i64 1
TBAA: remove !tbaa from testing cases when they are not needed. llvm-svn: 191689
2013-10-01 02:17:35 +08:00
store i32 %2, i32* %arrayidx3, align 4
PPC: Support dynamic allocas with large alignment Support for dynamic stack alignments in the PPC backend has been unfinished, in part because it depends on dynamic stack realignment (which I only just recently implemented fully). Now we can also support dynamic allocas with higher than the default target stack alignment (16 bytes). In order to round-up the requested size to the maximum requested alignment, we need an additional register to hold the rounded-up size. We're already using one scavenged register to hold the previous stack-pointer value (which needs to be stored with the signal-safe stdux update), and so when we have dynamic allocas and a large alignment, we allocate two emergency spill slots for the scavenger. llvm-svn: 186562
2013-07-18 12:28:21 +08:00
call void @bar(i32* %vla1, i32* %vla) #0
ret void
; CHECK-LABEL: @goo
; CHECK-DAG: li [[REG1:[0-9]+]], -128
; CHECK-DAG: neg [[REG2:[0-9]+]],
; CHECK: and [[REG1]], [[REG2]], [[REG1]]
; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]
; CHECK: blr
}
attributes #0 = { nounwind }