2015-11-24 05:33:58 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2015-10-11 06:21:05 +08:00
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+xop | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
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;
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; Equal
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;
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define <2 x i64> @eq_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
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; SSE2-LABEL: eq_v2i64:
|
2017-12-05 01:18:51 +08:00
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; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
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; SSE2-NEXT: pand %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: eq_v2i64:
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2017-12-05 01:18:51 +08:00
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; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; SSE41-NEXT: pcmpeqq %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; SSE42-LABEL: eq_v2i64:
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2017-12-05 01:18:51 +08:00
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; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; SSE42-NEXT: pcmpeqq %xmm1, %xmm0
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: eq_v2i64:
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2017-12-05 01:18:51 +08:00
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; AVX: # %bb.0:
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2015-10-11 06:21:05 +08:00
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; AVX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; XOP-LABEL: eq_v2i64:
|
2017-12-05 01:18:51 +08:00
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; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
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; XOP-NEXT: vpcomeqq %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
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; XOP-NEXT: retq
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%1 = icmp eq <2 x i64> %a, %b
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%2 = sext <2 x i1> %1 to <2 x i64>
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ret <2 x i64> %2
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}
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define <4 x i32> @eq_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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; SSE-LABEL: eq_v4i32:
|
2017-12-05 01:18:51 +08:00
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; SSE: # %bb.0:
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2015-10-11 06:21:05 +08:00
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; SSE-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: eq_v4i32:
|
2017-12-05 01:18:51 +08:00
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; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; XOP-LABEL: eq_v4i32:
|
2017-12-05 01:18:51 +08:00
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; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
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; XOP-NEXT: vpcomeqd %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
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; XOP-NEXT: retq
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%1 = icmp eq <4 x i32> %a, %b
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%2 = sext <4 x i1> %1 to <4 x i32>
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ret <4 x i32> %2
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}
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define <8 x i16> @eq_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
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; SSE-LABEL: eq_v8i16:
|
2017-12-05 01:18:51 +08:00
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; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; SSE-NEXT: pcmpeqw %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: eq_v8i16:
|
2017-12-05 01:18:51 +08:00
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; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; XOP-LABEL: eq_v8i16:
|
2017-12-05 01:18:51 +08:00
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; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
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; XOP-NEXT: vpcomeqw %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
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; XOP-NEXT: retq
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%1 = icmp eq <8 x i16> %a, %b
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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}
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define <16 x i8> @eq_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; SSE-LABEL: eq_v16i8:
|
2017-12-05 01:18:51 +08:00
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; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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; SSE-NEXT: pcmpeqb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: eq_v16i8:
|
2017-12-05 01:18:51 +08:00
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|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
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|
; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; XOP-LABEL: eq_v16i8:
|
2017-12-05 01:18:51 +08:00
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|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
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; XOP-NEXT: vpcomeqb %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
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; XOP-NEXT: retq
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%1 = icmp eq <16 x i8> %a, %b
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%2 = sext <16 x i1> %1 to <16 x i8>
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ret <16 x i8> %2
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}
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;
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; Not Equal
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|
;
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define <2 x i64> @ne_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
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; SSE2-LABEL: ne_v2i64:
|
2017-12-05 01:18:51 +08:00
|
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|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
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; SSE2-NEXT: pand %xmm1, %xmm0
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; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE2-NEXT: pxor %xmm1, %xmm0
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; SSE2-NEXT: retq
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|
|
;
|
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|
|
; SSE41-LABEL: ne_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: pcmpeqq %xmm1, %xmm0
|
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|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
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|
; SSE41-NEXT: pxor %xmm1, %xmm0
|
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; SSE41-NEXT: retq
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|
|
;
|
|
|
|
; SSE42-LABEL: ne_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: pcmpeqq %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
; SSE42-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ne_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ne_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomneqq %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ne <2 x i64> %a, %b
|
|
|
|
%2 = sext <2 x i1> %1 to <2 x i64>
|
|
|
|
ret <2 x i64> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @ne_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
|
|
|
; SSE-LABEL: ne_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
; SSE-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ne_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ne_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomneqd %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ne <4 x i32> %a, %b
|
|
|
|
%2 = sext <4 x i1> %1 to <4 x i32>
|
|
|
|
ret <4 x i32> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @ne_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
|
|
|
; SSE-LABEL: ne_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
; SSE-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ne_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ne_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomneqw %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ne <8 x i16> %a, %b
|
|
|
|
%2 = sext <8 x i1> %1 to <8 x i16>
|
|
|
|
ret <8 x i16> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i8> @ne_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
|
|
|
; SSE-LABEL: ne_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: pcmpeqb %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
; SSE-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ne_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ne_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomneqb %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ne <16 x i8> %a, %b
|
|
|
|
%2 = sext <16 x i1> %1 to <16 x i8>
|
|
|
|
ret <16 x i8> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
;
|
|
|
|
; Greater Than Or Equal
|
|
|
|
;
|
|
|
|
|
|
|
|
define <2 x i64> @ge_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
|
|
|
; SSE2-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
|
|
|
|
; SSE2-NEXT: pand %xmm3, %xmm0
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
|
|
|
; SSE2-NEXT: por %xmm0, %xmm1
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE41-NEXT: movdqa %xmm1, %xmm2
|
|
|
|
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
|
|
|
|
; SSE41-NEXT: pand %xmm3, %xmm0
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
|
|
|
; SSE41-NEXT: por %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm0, %xmm0
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE42-NEXT: pxor %xmm1, %xmm2
|
|
|
|
; SSE42-NEXT: pcmpgtq %xmm0, %xmm2
|
|
|
|
; SSE42-NEXT: pcmpeqd %xmm0, %xmm0
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX1-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX1: # %bb.0:
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX2: # %bb.0:
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: retq
|
2015-10-11 06:21:05 +08:00
|
|
|
;
|
|
|
|
; XOP-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgeuq %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
2017-12-04 15:21:01 +08:00
|
|
|
;
|
|
|
|
; AVX512-LABEL: ge_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX512: # %bb.0:
|
2017-12-07 18:40:31 +08:00
|
|
|
; AVX512-NEXT: # kill: def %xmm1 killed %xmm1 def %zmm1
|
|
|
|
; AVX512-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm1
|
|
|
|
; AVX512-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX512-NEXT: vzeroupper
|
|
|
|
; AVX512-NEXT: retq
|
2015-10-11 06:21:05 +08:00
|
|
|
%1 = icmp uge <2 x i64> %a, %b
|
|
|
|
%2 = sext <2 x i1> %1 to <2 x i64>
|
|
|
|
ret <2 x i64> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @ge_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
|
|
|
; SSE2-LABEL: ge_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm2
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: ge_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: pmaxud %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: ge_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: pmaxud %xmm0, %xmm1
|
|
|
|
; SSE42-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ge_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ge_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgeud %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp uge <4 x i32> %a, %b
|
|
|
|
%2 = sext <4 x i1> %1 to <4 x i32>
|
|
|
|
ret <4 x i32> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @ge_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
|
|
|
; SSE2-LABEL: ge_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: psubusw %xmm0, %xmm1
|
|
|
|
; SSE2-NEXT: pxor %xmm0, %xmm0
|
|
|
|
; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: ge_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: pmaxuw %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: ge_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: pmaxuw %xmm0, %xmm1
|
|
|
|
; SSE42-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ge_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ge_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgeuw %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp uge <8 x i16> %a, %b
|
|
|
|
%2 = sext <8 x i1> %1 to <8 x i16>
|
|
|
|
ret <8 x i16> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i8> @ge_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
|
|
|
; SSE-LABEL: ge_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: pmaxub %xmm0, %xmm1
|
|
|
|
; SSE-NEXT: pcmpeqb %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: ge_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: ge_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgeub %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp uge <16 x i8> %a, %b
|
|
|
|
%2 = sext <16 x i1> %1 to <16 x i8>
|
|
|
|
ret <16 x i8> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
;
|
|
|
|
; Greater Than
|
|
|
|
;
|
|
|
|
|
|
|
|
define <2 x i64> @gt_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
|
|
|
; SSE2-LABEL: gt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm2
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
|
|
|
|
; SSE2-NEXT: pand %xmm3, %xmm1
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
|
|
|
|
; SSE2-NEXT: por %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: gt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE41-NEXT: movdqa %xmm0, %xmm2
|
|
|
|
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
|
|
|
|
; SSE41-NEXT: pand %xmm3, %xmm1
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
|
|
|
|
; SSE41-NEXT: por %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: gt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE42-NEXT: pcmpgtq %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: gt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: gt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgtuq %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ugt <2 x i64> %a, %b
|
|
|
|
%2 = sext <2 x i1> %1 to <2 x i64>
|
|
|
|
ret <2 x i64> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @gt_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
|
|
|
; SSE-LABEL: gt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: pcmpgtd %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX1-LABEL: gt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX1: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: gt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX2: # %bb.0:
|
2017-07-16 19:43:16 +08:00
|
|
|
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
;
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-LABEL: gt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgtud %xmm1, %xmm0, %xmm0
|
|
|
|
; XOP-NEXT: retq
|
2015-10-11 06:21:05 +08:00
|
|
|
;
|
|
|
|
; AVX512-LABEL: gt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX512: # %bb.0:
|
2017-07-16 19:43:16 +08:00
|
|
|
; AVX512-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX512-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX512-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
%1 = icmp ugt <4 x i32> %a, %b
|
|
|
|
%2 = sext <4 x i1> %1 to <4 x i32>
|
|
|
|
ret <4 x i32> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @gt_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
|
|
|
; SSE-LABEL: gt_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: pcmpgtw %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: gt_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: gt_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgtuw %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ugt <8 x i16> %a, %b
|
|
|
|
%2 = sext <8 x i1> %1 to <8 x i16>
|
|
|
|
ret <8 x i16> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i8> @gt_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
|
|
|
; SSE-LABEL: gt_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: pcmpgtb %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: gt_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: gt_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomgtub %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ugt <16 x i8> %a, %b
|
|
|
|
%2 = sext <16 x i1> %1 to <16 x i8>
|
|
|
|
ret <16 x i8> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
;
|
|
|
|
; Less Than Or Equal
|
|
|
|
;
|
|
|
|
|
|
|
|
define <2 x i64> @le_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
|
|
|
; SSE2-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm2
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
|
|
; SSE2-NEXT: pand %xmm3, %xmm0
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
|
|
|
; SSE2-NEXT: por %xmm0, %xmm1
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE41-NEXT: movdqa %xmm0, %xmm2
|
|
|
|
; SSE41-NEXT: pcmpgtd %xmm1, %xmm2
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
|
|
; SSE41-NEXT: pand %xmm3, %xmm0
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
|
|
|
; SSE41-NEXT: por %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm0, %xmm0
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE42-NEXT: pcmpgtq %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
; SSE42-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX1-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX1: # %bb.0:
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX2: # %bb.0:
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: retq
|
2015-10-11 06:21:05 +08:00
|
|
|
;
|
|
|
|
; XOP-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomleuq %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
2017-12-04 15:21:01 +08:00
|
|
|
;
|
|
|
|
; AVX512-LABEL: le_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX512: # %bb.0:
|
2017-12-07 18:40:31 +08:00
|
|
|
; AVX512-NEXT: # kill: def %xmm1 killed %xmm1 def %zmm1
|
|
|
|
; AVX512-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
|
2017-12-04 15:21:01 +08:00
|
|
|
; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm1
|
|
|
|
; AVX512-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX512-NEXT: vzeroupper
|
|
|
|
; AVX512-NEXT: retq
|
2015-10-11 06:21:05 +08:00
|
|
|
%1 = icmp ule <2 x i64> %a, %b
|
|
|
|
%2 = sext <2 x i1> %1 to <2 x i64>
|
|
|
|
ret <2 x i64> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @le_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
|
|
|
; SSE2-LABEL: le_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: le_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: pminud %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: le_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: pminud %xmm0, %xmm1
|
|
|
|
; SSE42-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: le_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: le_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomleud %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ule <4 x i32> %a, %b
|
|
|
|
%2 = sext <4 x i1> %1 to <4 x i32>
|
|
|
|
ret <4 x i32> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @le_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
|
|
|
; SSE2-LABEL: le_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: psubusw %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm1
|
|
|
|
; SSE2-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: le_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: pminuw %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: le_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: pminuw %xmm0, %xmm1
|
|
|
|
; SSE42-NEXT: pcmpeqw %xmm1, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: le_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: le_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomleuw %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ule <8 x i16> %a, %b
|
|
|
|
%2 = sext <8 x i1> %1 to <8 x i16>
|
|
|
|
ret <8 x i16> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i8> @le_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
|
|
|
; SSE-LABEL: le_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: pminub %xmm0, %xmm1
|
|
|
|
; SSE-NEXT: pcmpeqb %xmm1, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: le_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: le_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomleub %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ule <16 x i8> %a, %b
|
|
|
|
%2 = sext <16 x i1> %1 to <16 x i8>
|
|
|
|
ret <16 x i8> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
;
|
|
|
|
; Less Than
|
|
|
|
;
|
|
|
|
|
|
|
|
define <2 x i64> @lt_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
|
|
|
|
; SSE2-LABEL: lt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
|
|
|
; SSE2-NEXT: pand %xmm3, %xmm1
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
|
|
|
|
; SSE2-NEXT: por %xmm1, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: lt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm1
|
|
|
|
; SSE41-NEXT: movdqa %xmm1, %xmm2
|
|
|
|
; SSE41-NEXT: pcmpgtd %xmm0, %xmm2
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm0, %xmm1
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
|
|
|
; SSE41-NEXT: pand %xmm3, %xmm1
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
|
|
|
|
; SSE41-NEXT: por %xmm1, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE42-LABEL: lt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE42: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; SSE42-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE42-NEXT: pxor %xmm1, %xmm2
|
|
|
|
; SSE42-NEXT: pcmpgtq %xmm0, %xmm2
|
|
|
|
; SSE42-NEXT: movdqa %xmm2, %xmm0
|
|
|
|
; SSE42-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: lt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: lt_v2i64:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomltuq %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ult <2 x i64> %a, %b
|
|
|
|
%2 = sext <2 x i1> %1 to <2 x i64>
|
|
|
|
ret <2 x i64> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @lt_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
|
|
|
; SSE-LABEL: lt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: pxor %xmm1, %xmm2
|
|
|
|
; SSE-NEXT: pcmpgtd %xmm0, %xmm2
|
|
|
|
; SSE-NEXT: movdqa %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX1-LABEL: lt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX1: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX1-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: lt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX2: # %bb.0:
|
2017-07-16 19:43:16 +08:00
|
|
|
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX2-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
;
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-LABEL: lt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomltud %xmm1, %xmm0, %xmm0
|
|
|
|
; XOP-NEXT: retq
|
2015-10-11 06:21:05 +08:00
|
|
|
;
|
|
|
|
; AVX512-LABEL: lt_v4i32:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX512: # %bb.0:
|
2017-07-16 19:43:16 +08:00
|
|
|
; AVX512-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX512-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX512-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
%1 = icmp ult <4 x i32> %a, %b
|
|
|
|
%2 = sext <4 x i1> %1 to <4 x i32>
|
|
|
|
ret <4 x i32> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @lt_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
|
|
|
|
; SSE-LABEL: lt_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: pxor %xmm1, %xmm2
|
|
|
|
; SSE-NEXT: pcmpgtw %xmm0, %xmm2
|
|
|
|
; SSE-NEXT: movdqa %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: lt_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpgtw %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: lt_v8i16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomltuw %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ult <8 x i16> %a, %b
|
|
|
|
%2 = sext <8 x i1> %1 to <8 x i16>
|
|
|
|
ret <8 x i16> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <16 x i8> @lt_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
|
|
|
; SSE-LABEL: lt_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
; SSE-NEXT: pxor %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: pxor %xmm1, %xmm2
|
|
|
|
; SSE-NEXT: pcmpgtb %xmm0, %xmm2
|
|
|
|
; SSE-NEXT: movdqa %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: lt_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2015-10-11 06:21:05 +08:00
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vpcmpgtb %xmm0, %xmm1, %xmm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
;
|
|
|
|
; XOP-LABEL: lt_v16i8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; XOP: # %bb.0:
|
2015-10-11 22:15:17 +08:00
|
|
|
; XOP-NEXT: vpcomltub %xmm1, %xmm0, %xmm0
|
2015-10-11 06:21:05 +08:00
|
|
|
; XOP-NEXT: retq
|
|
|
|
%1 = icmp ult <16 x i8> %a, %b
|
|
|
|
%2 = sext <16 x i1> %1 to <16 x i8>
|
|
|
|
ret <16 x i8> %2
|
|
|
|
}
|