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llvm-project/llvm/lib/Target/Hexagon/HexagonIntrinsicsDerived.td

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Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
//===-- HexagonIntrinsicsDerived.td - Derived intrinsics ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Multiply 64-bit and use lower result
//
// Optimized with intrinisics accumulates
//
def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
Hexagon V5 intrinsics support. llvm-svn: 156631
2012-05-12 03:39:13 +08:00
(i64
[Hexagon] Adding word combine dot-new form and replacing old combine opcode. llvm-svn: 223815
2014-12-10 03:23:45 +08:00
(A2_combinew
[Hexagon] Deleting a lot of old variants of intrinsics and updating references. llvm-svn: 227338
2015-01-29 02:29:11 +08:00
(M2_maci
(M2_maci
Hexagon V5 intrinsics support. llvm-svn: 156631
2012-05-12 03:39:13 +08:00
(i32
(EXTRACT_SUBREG
(i64
[Hexagon] Removing old multiply defs and updating references to new versions. llvm-svn: 224340
2014-12-17 00:10:01 +08:00
(M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
[Hexagon] Separate Hexagon subreg indices for different register classes For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
2016-11-10 00:19:08 +08:00
isub_lo)),
Hexagon V5 intrinsics support. llvm-svn: 156631
2012-05-12 03:39:13 +08:00
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
[Hexagon] Separate Hexagon subreg indices for different register classes For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
2016-11-10 00:19:08 +08:00
isub_lo)))),
isub_hi)),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_hi))),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_lo)),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_hi))),
Hexagon V5 intrinsics support. llvm-svn: 156631
2012-05-12 03:39:13 +08:00
(i32
(EXTRACT_SUBREG
(i64
[Hexagon] Removing old multiply defs and updating references to new versions. llvm-svn: 224340
2014-12-17 00:10:01 +08:00
(M2_dpmpyuu_s0
[Hexagon] Separate Hexagon subreg indices for different register classes For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
2016-11-10 00:19:08 +08:00
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
Hexagon V5 intrinsics support. llvm-svn: 156631
2012-05-12 03:39:13 +08:00
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
[Hexagon] Separate Hexagon subreg indices for different register classes For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
2016-11-10 00:19:08 +08:00
isub_lo)))), isub_lo))))>;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00