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llvm-project/llvm/test/TableGen/dag-isel-regclass-emit-enum.td

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[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705
2020-05-05 22:42:23 +08:00
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
def TestTargetInstrInfo : InstrInfo;
def TestTarget : Target {
let InstructionSet = TestTargetInstrInfo;
}
let Namespace = "TestNamespace" in {
def R0 : Register<"r0">;
Update TableGen test files to use the new '...' range punctuation.
2020-09-11 22:26:26 +08:00
foreach i = 0...127 in {
[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705
2020-05-05 22:42:23 +08:00
def GPR#i : RegisterClass<"TestTarget", [i32], 32,
(add R0)>;
}
def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
(add R0)>;
} // end Namespace TestNamespace
// CHECK: OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
// CHECK-NEXT: OPC_Scope, 14, /*->20*/ // 2 children in Scope
// CHECK-NEXT: OPC_CheckChild1Integer, 0,
// CHECK-NEXT: OPC_EmitInteger, MVT::i32, 0|128,1/*128*/,
// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 0))),
(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
// CHECK: OPC_CheckChild1Integer, 1,
// CHECK-NEXT: OPC_EmitInteger, MVT::i32, TestNamespace::GPR127RegClassID,
// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
def : Pat<(i32 (add i32:$src, (i32 1))),
(COPY_TO_REGCLASS GPR127, GPR0:$src)>;