2017-10-20 05:37:38 +08:00
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//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2017-10-20 05:37:38 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that RISCV uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#include "RISCV.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetLowering.h"
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2017-10-20 05:37:38 +08:00
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namespace llvm {
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class RISCVSubtarget;
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namespace RISCVISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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2017-11-08 21:41:21 +08:00
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RET_FLAG,
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[RISCV] Add support for _interrupt attribute
- Save/restore only registers that are used.
This includes Callee saved registers and Caller saved registers
(arguments and temporaries) for integer and FP registers.
- If there is a call in the interrupt handler, save/restore all
Caller saved registers (arguments and temporaries) and all FP registers.
- Emit special return instructions depending on "interrupt"
attribute type.
Based on initial patch by Zhaoshi Zheng.
Reviewers: asb
Reviewed By: asb
Subscribers: rkruppe, the_o, MartinMosbeck, brucehoult, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, llvm-commits
Differential Revision: https://reviews.llvm.org/D48411
llvm-svn: 338047
2018-07-27 01:49:43 +08:00
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URET_FLAG,
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SRET_FLAG,
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MRET_FLAG,
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2017-11-21 15:51:32 +08:00
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CALL,
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2018-04-12 13:34:25 +08:00
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SELECT_CC,
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BuildPairF64,
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2018-05-24 06:44:08 +08:00
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SplitF64,
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2019-01-25 13:04:00 +08:00
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TAIL,
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// RV64I shifts, directly matching the semantics of the named RISC-V
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// instructions.
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SLLW,
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SRAW,
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2019-01-25 13:11:34 +08:00
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SRLW,
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// 32-bit operations from RV64M that can't be simply matched with a pattern
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// at instruction selection time.
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DIVW,
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DIVUW,
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2019-02-01 06:48:38 +08:00
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REMUW,
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2020-11-21 02:11:34 +08:00
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// RV64IB rotates, directly matching the semantics of the named RISC-V
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// instructions.
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ROLW,
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RORW,
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2020-11-26 01:43:16 +08:00
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// RV64IB funnel shifts, with the semantics of the named RISC-V instructions,
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// but the same operand order as fshl/fshr intrinsics.
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FSRW,
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FSLW,
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2020-07-03 22:57:59 +08:00
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// FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
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// XLEN is the only legal integer width.
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//
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2020-12-04 02:29:10 +08:00
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// FMV_H_X matches the semantics of the FMV.H.X.
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// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
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2020-07-03 22:57:59 +08:00
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// FMV_W_X_RV64 matches the semantics of the FMV.W.X.
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2019-02-01 06:48:38 +08:00
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// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
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2020-07-03 22:57:59 +08:00
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//
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2019-02-01 06:48:38 +08:00
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// This is a more convenient semantic for producing dagcombines that remove
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// unnecessary GPR->FPR->GPR moves.
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2020-12-04 02:29:10 +08:00
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FMV_H_X,
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FMV_X_ANYEXTH,
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2019-02-01 06:48:38 +08:00
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FMV_W_X_RV64,
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[RISCV] Support @llvm.readcyclecounter() Intrinsic
On RISC-V, the `cycle` CSR holds a 64-bit count of the number of clock
cycles executed by the core, from an arbitrary point in the past. This
matches the intended semantics of `@llvm.readcyclecounter()`, which we
currently leave to the default lowering (to the constant 0).
With this patch, we will now correctly lower this intrinsic to the
intended semantics, using the user-space instruction `rdcycle`. On
64-bit targets, we can directly lower to this instruction.
On 32-bit targets, we need to do more, as `rdcycle` only returns the low
32-bits of the `cycle` CSR. In this case, we perform a custom lowering,
based on the PowerPC lowering, using `rdcycleh` to obtain the high
32-bits of the `cycle` CSR. This custom lowering inserts a new basic
block which detects overflow in the high 32-bits of the `cycle` CSR
during reading (because multiple instructions are required to read). The
emitted assembly matches the suggested assembly in the RISC-V
specification.
Differential Revision: https://reviews.llvm.org/D64125
llvm-svn: 365201
2019-07-05 20:35:21 +08:00
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FMV_X_ANYEXTW_RV64,
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// READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
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// (returns (Lo, Hi)). It takes a chain operand.
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2020-11-11 21:41:55 +08:00
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READ_CYCLE_WIDE,
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// Generalized Reverse and Generalized Or-Combine - directly matching the
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// semantics of the named RISC-V instructions. Lowered as custom nodes as
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// TableGen chokes when faced with commutative permutations in deeply-nested
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// DAGs. Each node takes an input operand and a TargetConstant immediate
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// shift amount, and outputs a bit-manipulated version of input. All operands
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// are of type XLenVT.
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GREVI,
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GREVIW,
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GORCI,
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GORCIW,
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2017-10-20 05:37:38 +08:00
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};
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2020-11-11 21:41:55 +08:00
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} // namespace RISCVISD
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2017-10-20 05:37:38 +08:00
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class RISCVTargetLowering : public TargetLowering {
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const RISCVSubtarget &Subtarget;
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public:
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explicit RISCVTargetLowering(const TargetMachine &TM,
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const RISCVSubtarget &STI);
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2020-12-11 15:16:08 +08:00
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const RISCVSubtarget &getSubtarget() const { return Subtarget; }
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2018-09-19 18:54:22 +08:00
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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2018-04-26 20:13:48 +08:00
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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2018-04-26 21:15:17 +08:00
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bool isLegalICmpImmediate(int64_t Imm) const override;
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2018-04-26 21:00:37 +08:00
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bool isLegalAddImmediate(int64_t Imm) const override;
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2018-04-26 21:37:00 +08:00
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bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
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bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
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2018-04-26 22:04:18 +08:00
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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2018-11-30 17:56:54 +08:00
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bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
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2020-11-10 02:05:51 +08:00
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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2020-03-20 17:22:48 +08:00
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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[RISCV] Support Bit-Preserving FP in F/D Extensions
Summary:
This allows some integer bitwise operations to instead be performed by
hardware fp instructions. This is correct because the RISC-V spec
requires the F and D extensions to use the IEEE-754 standard
representation, and fp register loads and stores to be bit-preserving.
This is tested against the soft-float ABI, but with hardware float
extensions enabled, so that the tests also ensure the optimisation also
fires in this case.
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62900
llvm-svn: 362790
2019-06-07 20:20:14 +08:00
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bool hasBitPreservingFPLogic(EVT VT) const override;
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2018-04-26 20:13:48 +08:00
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2017-10-20 05:37:38 +08:00
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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2019-01-25 13:04:00 +08:00
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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2017-10-20 05:37:38 +08:00
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2018-10-04 07:30:16 +08:00
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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2019-01-25 13:04:00 +08:00
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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2017-10-20 05:37:38 +08:00
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// This method returns the name of a target specific DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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2018-01-11 04:05:09 +08:00
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[RISCV] Support 'f' Inline Assembly Constraint
Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).
This patch adds support in both the clang frontend, and LLVM itself.
Reviewers: asb, lewis-revill
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D65500
llvm-svn: 367403
2019-07-31 17:45:55 +08:00
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ConstraintType getConstraintType(StringRef Constraint) const override;
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2019-08-16 18:28:34 +08:00
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unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
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2018-01-11 04:05:09 +08:00
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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2017-10-20 05:37:38 +08:00
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2019-06-11 20:42:13 +08:00
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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2017-11-21 15:51:32 +08:00
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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2018-02-02 10:43:18 +08:00
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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2017-11-21 15:51:32 +08:00
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2019-03-22 18:39:22 +08:00
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bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
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return VT.isScalarInteger();
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}
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2020-05-02 22:05:12 +08:00
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bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
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2019-03-22 18:39:22 +08:00
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2018-06-13 20:04:51 +08:00
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bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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return isa<LoadInst>(I) || isa<StoreInst>(I);
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}
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Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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2020-11-26 07:07:34 +08:00
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT VT) const override;
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2019-03-12 05:41:22 +08:00
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ISD::NodeType getExtendForAtomicOps() const override {
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[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
Summary:
Currently, the comparison argument used for ATOMIC_CMP_XCHG is legalised
with GetPromotedInteger, which leaves the upper bits of the value
undefind. Since this is used for comparing in an LR/SC loop with a
full-width comparison, we must sign extend it. We introduce a new
getExtendForAtomicCmpSwapArg to complement getExtendForAtomicOps, since
many targets have compare-and-swap instructions (or pseudos) that
correctly handle an any-extend input, and the existing function
determines the extension of the result, whereas we are concerned with
the input.
This is related to https://reviews.llvm.org/D58829, which solved the
issue for ATOMIC_CMP_SWAP_WITH_SUCCESS, but not the simpler
ATOMIC_CMP_SWAP.
Reviewers: asb, lenary, efriedma
Reviewed By: asb
Subscribers: arichardson, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, evandro, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74453
2020-04-01 22:50:47 +08:00
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return ISD::SIGN_EXTEND;
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}
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ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
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2019-03-12 05:41:22 +08:00
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return ISD::SIGN_EXTEND;
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}
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2019-04-16 22:38:32 +08:00
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bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return false;
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return true;
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}
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[RISCV] Prevent re-ordering some adds after shifts
Summary:
DAGCombine will normally turn a `(shl (add x, c1), c2)` into `(add (shl x, c2), c1 << c2)`, where `c1` and `c2` are constants. This can be prevented by a callback in TargetLowering.
On RISC-V, materialising the constant `c1 << c2` can be more expensive than materialising `c1`, because materialising the former may take more instructions, and may use a register, where materialising the latter would not.
This patch implements the hook in RISCVTargetLowering to prevent this transform, in the cases where:
- `c1` fits into the immediate field in an `addi` instruction.
- `c1` takes fewer instructions to materialise than `c1 << c2`.
In future, DAGCombine could do the check to see whether `c1` fits into an add immediate, which might simplify more targets hooks than just RISC-V.
Reviewers: asb, luismarques, efriedma
Reviewed By: asb
Subscribers: xbolva00, lebedev.ri, craig.topper, lewis-revill, Jim, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62857
llvm-svn: 363736
2019-06-19 04:38:08 +08:00
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bool isDesirableToCommuteWithShift(const SDNode *N,
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CombineLevel Level) const override;
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2019-04-16 22:38:32 +08:00
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2019-07-08 17:16:47 +08:00
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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2020-04-08 22:29:30 +08:00
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Register
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2019-07-08 17:16:47 +08:00
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getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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2020-04-08 22:29:30 +08:00
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Register
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2019-07-08 17:16:47 +08:00
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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2019-08-29 07:40:37 +08:00
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bool shouldExtendTypeInLibCall(EVT Type) const override;
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2019-11-04 19:21:51 +08:00
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/// Returns the register with the specified architectural or ABI name. This
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/// method is necessary to lower the llvm.read_register.* and
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/// llvm.write_register.* intrinsics. Allocatable registers must be reserved
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/// with the clang -ffixed-xX flag for access to be allowed.
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2019-12-28 22:18:56 +08:00
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Register getRegisterByName(const char *RegName, LLT VT,
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2019-11-04 19:21:51 +08:00
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const MachineFunction &MF) const override;
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2017-10-20 05:37:38 +08:00
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// Lower incoming arguments, copy physregs into vregs
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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2020-05-12 18:49:17 +08:00
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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2017-10-20 05:37:38 +08:00
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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2017-11-08 21:41:21 +08:00
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
|
2020-06-10 16:16:09 +08:00
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2017-10-20 05:37:38 +08:00
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override {
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|
return true;
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}
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2020-02-18 23:53:26 +08:00
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
|
2020-06-10 16:16:09 +08:00
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bool shouldConsiderGEPOffsetSplit() const override { return true; }
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2020-07-08 09:48:46 +08:00
|
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bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
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SDValue C) const override;
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|
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2020-06-10 16:16:09 +08:00
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
|
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Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI,
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Value *AlignedAddr, Value *Incr,
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Value *Mask, Value *ShiftAmt,
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AtomicOrdering Ord) const override;
|
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|
TargetLowering::AtomicExpansionKind
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shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
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Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder,
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AtomicCmpXchgInst *CI,
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Value *AlignedAddr, Value *CmpVal,
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Value *NewVal, Value *Mask,
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|
AtomicOrdering Ord) const override;
|
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|
private:
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|
|
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
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|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
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|
|
bool IsRet) const;
|
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|
|
void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
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|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
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|
|
bool IsRet, CallLoweringInfo *CLI) const;
|
2019-04-01 22:42:56 +08:00
|
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|
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|
|
template <class NodeTy>
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2019-06-11 20:57:47 +08:00
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|
|
SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
|
2019-04-01 22:42:56 +08:00
|
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|
|
2019-06-19 16:40:59 +08:00
|
|
|
SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
|
|
|
|
bool UseGOT) const;
|
|
|
|
SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
|
|
|
|
|
2017-11-08 21:24:21 +08:00
|
|
|
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
2017-11-21 16:11:03 +08:00
|
|
|
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
2018-03-20 21:26:12 +08:00
|
|
|
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
2019-06-19 16:40:59 +08:00
|
|
|
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
2017-11-21 15:51:32 +08:00
|
|
|
SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
2018-01-11 03:41:03 +08:00
|
|
|
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
2018-10-04 13:27:50 +08:00
|
|
|
SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
2019-04-16 22:38:32 +08:00
|
|
|
SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
|
2020-03-28 08:27:00 +08:00
|
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
2020-12-17 13:45:52 +08:00
|
|
|
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
2018-05-24 06:44:08 +08:00
|
|
|
|
2019-02-21 22:31:41 +08:00
|
|
|
bool isEligibleForTailCallOptimization(
|
|
|
|
CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
|
|
|
|
const SmallVector<CCValAssign, 16> &ArgLocs) const;
|
2018-09-19 18:54:22 +08:00
|
|
|
|
2019-10-23 04:25:01 +08:00
|
|
|
/// Generate error diagnostics if any register used by CC has been marked
|
|
|
|
/// reserved.
|
|
|
|
void validateCCReservedRegs(
|
|
|
|
const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
|
|
|
|
MachineFunction &MF) const;
|
2017-10-20 05:37:38 +08:00
|
|
|
};
|
2020-12-11 15:16:08 +08:00
|
|
|
|
|
|
|
namespace RISCVVIntrinsicsTable {
|
|
|
|
|
|
|
|
struct RISCVVIntrinsicInfo {
|
|
|
|
unsigned int IntrinsicID;
|
|
|
|
unsigned int ExtendedOperand;
|
|
|
|
};
|
|
|
|
|
|
|
|
using namespace RISCV;
|
|
|
|
|
|
|
|
#define GET_RISCVVIntrinsicsTable_DECL
|
|
|
|
#include "RISCVGenSearchableTables.inc"
|
|
|
|
|
|
|
|
} // end namespace RISCVVIntrinsicsTable
|
2017-10-20 05:37:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|