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llvm-project/llvm/test/CodeGen/Mips/brcongt.ll

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[BPI] Improve static heuristics for integer comparisons Similarly as for pointers, even for integers a == b is usually false. GCC also uses this heuristic. Reviewed By: ebrevnov Differential Revision: https://reviews.llvm.org/D85781
2020-08-13 18:45:14 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
2015-10-15 22:34:23 +08:00
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
Add conditional branch instructions and their patterns. llvm-svn: 166134
2012-10-18 06:29:54 +08:00
@i = global i32 5, align 4
@j = global i32 10, align 4
@k = global i32 5, align 4
@result = global i32 0, align 4
define void @test() nounwind {
[BPI] Improve static heuristics for integer comparisons Similarly as for pointers, even for integers a == b is usually false. GCC also uses this heuristic. Reviewed By: ebrevnov Differential Revision: https://reviews.llvm.org/D85781
2020-08-13 18:45:14 +08:00
; 16-LABEL: test:
; 16: # %bb.0: # %entry
; 16-NEXT: lui $2, %hi(_gp_disp)
; 16-NEXT: addiu $2, $2, %lo(_gp_disp)
; 16-NEXT: li $2, %hi(_gp_disp)
; 16-NEXT: addiu $3, $pc, %lo(_gp_disp)
; 16-NEXT: sll $2, $2, 16
; 16-NEXT: addu $2, $3, $2
; 16-NEXT: lw $3, %got(i)($2)
; 16-NEXT: lw $4, %got(j)($2)
; 16-NEXT: lw $3, 0($3)
; 16-NEXT: lw $4, 0($4)
; 16-NEXT: slt $4, $3
; 16-NEXT: bteqz $BB0_2 # 16 bit inst
; 16-NEXT: # %bb.1: # %if.end
; 16-NEXT: jrc $ra
; 16-NEXT: $BB0_2: # %if.then
; 16-NEXT: lw $2, %got(result)($2)
; 16-NEXT: li $3, 1
; 16-NEXT: sw $3, 0($2)
; 16-NEXT: jrc $ra
Add conditional branch instructions and their patterns. llvm-svn: 166134
2012-10-18 06:29:54 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @i, align 4
%1 = load i32, i32* @j, align 4
Revert "CodeGen: Allow small copyable blocks to "break" the CFG." This reverts commit ada6595a526d71df04988eb0a4b4fe84df398ded. This needs a simple probability check because there are some cases where it is not profitable. llvm-svn: 291695
2017-01-12 03:55:19 +08:00
%cmp = icmp sgt i32 %0, %1
br i1 %cmp, label %if.end, label %if.then
Add conditional branch instructions and their patterns. llvm-svn: 166134
2012-10-18 06:29:54 +08:00
if.then: ; preds = %entry
store i32 1, i32* @result, align 4
br label %if.end
if.end: ; preds = %entry, %if.then
ret void
}