2016-01-04 01:33:32 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2017-06-29 19:08:11 +08:00
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|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
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|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
|
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|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
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|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
|
2018-01-10 00:26:06 +08:00
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|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX,AVX2,AVX2-SLOW
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|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=ALL,AVX,AVX2,AVX2-FAST
|
2016-01-04 01:33:32 +08:00
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|
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define <2 x double> @insert_v2f64_z1(<2 x double> %a) {
|
2016-02-24 22:53:27 +08:00
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|
|
; SSE2-LABEL: insert_v2f64_z1:
|
2017-12-05 01:18:51 +08:00
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|
|
; SSE2: # %bb.0:
|
2016-02-24 22:53:27 +08:00
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|
|
; SSE2-NEXT: xorpd %xmm1, %xmm1
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|
|
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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|
; SSE2-NEXT: retq
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|
|
;
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|
; SSE3-LABEL: insert_v2f64_z1:
|
2017-12-05 01:18:51 +08:00
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|
|
; SSE3: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE3-NEXT: xorpd %xmm1, %xmm1
|
|
|
|
; SSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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|
|
|
; SSE3-NEXT: retq
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|
|
;
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|
; SSSE3-LABEL: insert_v2f64_z1:
|
2017-12-05 01:18:51 +08:00
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|
|
; SSSE3: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSSE3-NEXT: xorpd %xmm1, %xmm1
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|
; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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|
; SSSE3-NEXT: retq
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|
;
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|
; SSE41-LABEL: insert_v2f64_z1:
|
2017-12-05 01:18:51 +08:00
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|
|
; SSE41: # %bb.0:
|
2018-01-16 06:18:45 +08:00
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|
|
; SSE41-NEXT: xorps %xmm1, %xmm1
|
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|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: retq
|
2016-01-04 01:33:32 +08:00
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|
|
;
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|
|
|
; AVX-LABEL: insert_v2f64_z1:
|
2017-12-05 01:18:51 +08:00
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|
|
; AVX: # %bb.0:
|
2018-01-16 06:18:45 +08:00
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|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
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|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX-NEXT: retq
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|
|
%1 = insertelement <2 x double> %a, double 0.0, i32 0
|
|
|
|
ret <2 x double> %1
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|
|
}
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|
define <4 x double> @insert_v4f64_0zz3(<4 x double> %a) {
|
2016-02-24 22:53:27 +08:00
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|
|
; SSE2-LABEL: insert_v4f64_0zz3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2017-01-23 06:21:44 +08:00
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|
|
; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
|
2016-02-24 22:53:27 +08:00
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|
|
; SSE2-NEXT: xorpd %xmm2, %xmm2
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|
|
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
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|
; SSE2-NEXT: retq
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|
|
;
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|
; SSE3-LABEL: insert_v4f64_0zz3:
|
2017-12-05 01:18:51 +08:00
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|
|
; SSE3: # %bb.0:
|
2017-01-23 06:21:44 +08:00
|
|
|
; SSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE3-NEXT: xorpd %xmm2, %xmm2
|
|
|
|
; SSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
|
|
|
|
; SSE3-NEXT: retq
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|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v4f64_0zz3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2017-01-23 06:21:44 +08:00
|
|
|
; SSSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSSE3-NEXT: xorpd %xmm2, %xmm2
|
|
|
|
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
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|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v4f64_0zz3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
|
2018-01-16 06:18:45 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3]
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: insert_v4f64_0zz3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2018-01-16 06:18:45 +08:00
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
%1 = insertelement <4 x double> %a, double 0.0, i32 1
|
|
|
|
%2 = insertelement <4 x double> %1, double 0.0, i32 2
|
|
|
|
ret <4 x double> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <2 x i64> @insert_v2i64_z1(<2 x i64> %a) {
|
|
|
|
; SSE2-LABEL: insert_v2i64_z1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: xorpd %xmm1, %xmm1
|
|
|
|
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v2i64_z1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: xorpd %xmm1, %xmm1
|
|
|
|
; SSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v2i64_z1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: xorpd %xmm1, %xmm1
|
|
|
|
; SSSE3-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v2i64_z1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2018-01-16 06:18:45 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm1, %xmm1
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
2018-01-16 06:18:45 +08:00
|
|
|
; AVX-LABEL: insert_v2i64_z1:
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
|
|
|
|
; AVX-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <2 x i64> %a, i64 0, i32 0
|
|
|
|
ret <2 x i64> %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i64> @insert_v4i64_01z3(<4 x i64> %a) {
|
|
|
|
; SSE2-LABEL: insert_v4i64_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: xorpd %xmm2, %xmm2
|
|
|
|
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v4i64_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: xorpd %xmm2, %xmm2
|
|
|
|
; SSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v4i64_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: xorpd %xmm2, %xmm2
|
|
|
|
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v4i64_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2018-01-16 06:18:45 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
2018-01-16 06:18:45 +08:00
|
|
|
; AVX-LABEL: insert_v4i64_01z3:
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
|
|
|
|
; AVX-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <4 x i64> %a, i64 0, i32 2
|
|
|
|
ret <4 x i64> %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x float> @insert_v4f32_01z3(<4 x float> %a) {
|
|
|
|
; SSE2-LABEL: insert_v4f32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: xorps %xmm1, %xmm1
|
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
|
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v4f32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: xorps %xmm1, %xmm1
|
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
|
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v4f32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: xorps %xmm1, %xmm1
|
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
|
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v4f32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm1, %xmm1
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: insert_v4f32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
2016-02-24 22:53:27 +08:00
|
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
%1 = insertelement <4 x float> %a, float 0.0, i32 2
|
|
|
|
ret <4 x float> %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @insert_v8f32_z12345z7(<8 x float> %a) {
|
|
|
|
; SSE2-LABEL: insert_v8f32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
|
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v8f32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
|
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v8f32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
|
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v8f32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: insert_v8f32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2017-07-28 01:47:01 +08:00
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
2016-02-24 23:14:21 +08:00
|
|
|
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
%1 = insertelement <8 x float> %a, float 0.0, i32 0
|
|
|
|
%2 = insertelement <8 x float> %1, float 0.0, i32 6
|
|
|
|
ret <8 x float> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @insert_v4i32_01z3(<4 x i32> %a) {
|
|
|
|
; SSE2-LABEL: insert_v4i32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE2-NEXT: xorps %xmm1, %xmm1
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
|
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v4i32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE3-NEXT: xorps %xmm1, %xmm1
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
|
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v4i32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSSE3-NEXT: xorps %xmm1, %xmm1
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
|
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v4i32_01z3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2018-01-16 06:18:45 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm1, %xmm1
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
2018-01-16 06:18:45 +08:00
|
|
|
; AVX-LABEL: insert_v4i32_01z3:
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
|
|
|
|
; AVX-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <4 x i32> %a, i32 0, i32 2
|
|
|
|
ret <4 x i32> %1
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i32> @insert_v8i32_z12345z7(<8 x i32> %a) {
|
|
|
|
; SSE2-LABEL: insert_v8i32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE2-NEXT: xorps %xmm2, %xmm2
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
|
|
|
|
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v8i32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE3-NEXT: xorps %xmm2, %xmm2
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
|
|
|
|
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v8i32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSSE3-NEXT: xorps %xmm2, %xmm2
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
|
|
|
|
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v8i32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2018-01-16 06:18:45 +08:00
|
|
|
; SSE41-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3]
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2],xmm1[3]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
2017-09-04 01:52:23 +08:00
|
|
|
; AVX-LABEL: insert_v8i32_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2017-09-04 01:52:23 +08:00
|
|
|
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5],ymm1[6],ymm0[7]
|
|
|
|
; AVX-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <8 x i32> %a, i32 0, i32 0
|
|
|
|
%2 = insertelement <8 x i32> %1, i32 0, i32 6
|
|
|
|
ret <8 x i32> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x i16> @insert_v8i16_z12345z7(<8 x i16> %a) {
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE2-LABEL: insert_v8i16_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE2-NEXT: xorl %eax, %eax
|
|
|
|
; SSE2-NEXT: pinsrw $0, %eax, %xmm0
|
|
|
|
; SSE2-NEXT: pinsrw $6, %eax, %xmm0
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v8i16_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE3-NEXT: xorl %eax, %eax
|
|
|
|
; SSE3-NEXT: pinsrw $0, %eax, %xmm0
|
|
|
|
; SSE3-NEXT: pinsrw $6, %eax, %xmm0
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v8i16_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSSE3-NEXT: xorl %eax, %eax
|
|
|
|
; SSSE3-NEXT: pinsrw $0, %eax, %xmm0
|
|
|
|
; SSSE3-NEXT: pinsrw $6, %eax, %xmm0
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v8i16_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm1
|
2016-02-24 23:14:21 +08:00
|
|
|
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5],xmm1[6],xmm0[7]
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
;
|
|
|
|
; AVX-LABEL: insert_v8i16_z12345z7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
2016-02-24 23:14:21 +08:00
|
|
|
; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5],xmm1[6],xmm0[7]
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
%1 = insertelement <8 x i16> %a, i16 0, i32 0
|
|
|
|
%2 = insertelement <8 x i16> %1, i16 0, i32 6
|
|
|
|
ret <8 x i16> %2
|
|
|
|
}
|
|
|
|
|
2017-06-20 18:24:06 +08:00
|
|
|
define <16 x i16> @insert_v16i16_z12345z789ABCDEz(<16 x i16> %a) {
|
|
|
|
; SSE2-LABEL: insert_v16i16_z12345z789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE2-NEXT: xorl %eax, %eax
|
|
|
|
; SSE2-NEXT: pinsrw $0, %eax, %xmm0
|
|
|
|
; SSE2-NEXT: pinsrw $6, %eax, %xmm0
|
|
|
|
; SSE2-NEXT: pinsrw $7, %eax, %xmm1
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
2017-06-20 18:24:06 +08:00
|
|
|
; SSE3-LABEL: insert_v16i16_z12345z789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE3-NEXT: xorl %eax, %eax
|
|
|
|
; SSE3-NEXT: pinsrw $0, %eax, %xmm0
|
|
|
|
; SSE3-NEXT: pinsrw $6, %eax, %xmm0
|
|
|
|
; SSE3-NEXT: pinsrw $7, %eax, %xmm1
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
2017-06-20 18:24:06 +08:00
|
|
|
; SSSE3-LABEL: insert_v16i16_z12345z789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSSE3-NEXT: xorl %eax, %eax
|
|
|
|
; SSSE3-NEXT: pinsrw $0, %eax, %xmm0
|
|
|
|
; SSSE3-NEXT: pinsrw $6, %eax, %xmm0
|
|
|
|
; SSSE3-NEXT: pinsrw $7, %eax, %xmm1
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
2017-06-20 18:24:06 +08:00
|
|
|
; SSE41-LABEL: insert_v16i16_z12345z789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm2
|
2016-02-24 23:14:21 +08:00
|
|
|
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5],xmm2[6],xmm0[7]
|
2016-02-24 22:53:27 +08:00
|
|
|
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
|
|
|
|
; SSE41-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
;
|
2017-06-20 23:19:02 +08:00
|
|
|
; AVX-LABEL: insert_v16i16_z12345z789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2017-06-20 23:19:02 +08:00
|
|
|
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
|
|
|
|
; AVX-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <16 x i16> %a, i16 0, i32 0
|
|
|
|
%2 = insertelement <16 x i16> %1, i16 0, i32 6
|
|
|
|
%3 = insertelement <16 x i16> %2, i16 0, i32 15
|
|
|
|
ret <16 x i16> %3
|
|
|
|
}
|
|
|
|
|
2017-01-23 05:06:28 +08:00
|
|
|
define <16 x i8> @insert_v16i8_z123456789ABCDEz(<16 x i8> %a) {
|
|
|
|
; SSE2-LABEL: insert_v16i8_z123456789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
2017-01-23 05:06:28 +08:00
|
|
|
; SSE3-LABEL: insert_v16i8_z123456789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE3-NEXT: andps {{.*}}(%rip), %xmm0
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
2017-01-23 05:06:28 +08:00
|
|
|
; SSSE3-LABEL: insert_v16i8_z123456789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2017-01-23 06:21:44 +08:00
|
|
|
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
2017-01-23 05:06:28 +08:00
|
|
|
; SSE41-LABEL: insert_v16i8_z123456789ABCDEz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: xorl %eax, %eax
|
|
|
|
; SSE41-NEXT: pinsrb $0, %eax, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrb $15, %eax, %xmm0
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
2018-01-10 00:26:06 +08:00
|
|
|
; AVX1-LABEL: insert_v16i8_z123456789ABCDEz:
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
; AVX1-NEXT: xorl %eax, %eax
|
|
|
|
; AVX1-NEXT: vpinsrb $0, %eax, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-SLOW-LABEL: insert_v16i8_z123456789ABCDEz:
|
|
|
|
; AVX2-SLOW: # %bb.0:
|
|
|
|
; AVX2-SLOW-NEXT: xorl %eax, %eax
|
|
|
|
; AVX2-SLOW-NEXT: vpinsrb $0, %eax, %xmm0, %xmm0
|
|
|
|
; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
|
|
|
|
; AVX2-SLOW-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-FAST-LABEL: insert_v16i8_z123456789ABCDEz:
|
|
|
|
; AVX2-FAST: # %bb.0:
|
|
|
|
; AVX2-FAST-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
|
|
|
|
; AVX2-FAST-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <16 x i8> %a, i8 0, i32 0
|
|
|
|
%2 = insertelement <16 x i8> %1, i8 0, i32 15
|
|
|
|
ret <16 x i8> %2
|
|
|
|
}
|
|
|
|
|
|
|
|
define <32 x i8> @insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz(<32 x i8> %a) {
|
|
|
|
; SSE2-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE2: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0
|
2017-01-23 06:45:23 +08:00
|
|
|
; SSE2-NEXT: andps {{.*}}(%rip), %xmm1
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE3: # %bb.0:
|
2017-01-30 02:13:37 +08:00
|
|
|
; SSE3-NEXT: andps {{.*}}(%rip), %xmm0
|
2017-01-23 06:45:23 +08:00
|
|
|
; SSE3-NEXT: andps {{.*}}(%rip), %xmm1
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2017-01-23 06:21:44 +08:00
|
|
|
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0
|
|
|
|
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm1
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE41: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: xorl %eax, %eax
|
|
|
|
; SSE41-NEXT: pinsrb $0, %eax, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrb $15, %eax, %xmm0
|
2017-01-31 22:59:44 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm2
|
|
|
|
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
|
2016-01-04 01:33:32 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX1-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX1: # %bb.0:
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX1-NEXT: xorl %eax, %eax
|
|
|
|
; AVX1-NEXT: vpinsrb $0, %eax, %xmm0, %xmm1
|
2017-02-03 06:02:57 +08:00
|
|
|
; AVX1-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1
|
2017-02-12 06:57:12 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
2017-01-31 22:59:44 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
2017-02-12 06:57:12 +08:00
|
|
|
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
2016-01-04 01:33:32 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
2018-01-10 00:26:06 +08:00
|
|
|
; AVX2-SLOW-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
|
|
|
; AVX2-SLOW: # %bb.0:
|
|
|
|
; AVX2-SLOW-NEXT: xorl %eax, %eax
|
|
|
|
; AVX2-SLOW-NEXT: vpinsrb $0, %eax, %xmm0, %xmm1
|
|
|
|
; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1
|
|
|
|
; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm0
|
|
|
|
; AVX2-SLOW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
|
|
|
; AVX2-SLOW-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
|
|
|
|
; AVX2-SLOW-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX2-SLOW-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-FAST-LABEL: insert_v32i8_z123456789ABCDEzGHIJKLMNOPQRSTzz:
|
|
|
|
; AVX2-FAST: # %bb.0:
|
|
|
|
; AVX2-FAST-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
|
|
|
|
; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm0
|
|
|
|
; AVX2-FAST-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
|
|
|
; AVX2-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
|
|
|
|
; AVX2-FAST-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX2-FAST-NEXT: retq
|
2016-01-04 01:33:32 +08:00
|
|
|
%1 = insertelement <32 x i8> %a, i8 0, i32 0
|
|
|
|
%2 = insertelement <32 x i8> %1, i8 0, i32 15
|
|
|
|
%3 = insertelement <32 x i8> %2, i8 0, i32 30
|
|
|
|
%4 = insertelement <32 x i8> %3, i8 0, i32 31
|
|
|
|
ret <32 x i8> %4
|
|
|
|
}
|
2019-04-19 00:58:50 +08:00
|
|
|
|
|
|
|
; FIXME: Prefer 'movd' over 'pinsr' to element 0.
|
|
|
|
|
|
|
|
define <4 x i32> @PR41512(i32 %x, i32 %y) {
|
|
|
|
; SSE2-LABEL: PR41512:
|
|
|
|
; SSE2: # %bb.0:
|
|
|
|
; SSE2-NEXT: movd %edi, %xmm0
|
|
|
|
; SSE2-NEXT: movd %esi, %xmm1
|
|
|
|
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: PR41512:
|
|
|
|
; SSE3: # %bb.0:
|
|
|
|
; SSE3-NEXT: movd %edi, %xmm0
|
|
|
|
; SSE3-NEXT: movd %esi, %xmm1
|
|
|
|
; SSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: PR41512:
|
|
|
|
; SSSE3: # %bb.0:
|
|
|
|
; SSSE3-NEXT: movd %edi, %xmm0
|
|
|
|
; SSSE3-NEXT: movd %esi, %xmm1
|
|
|
|
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: PR41512:
|
|
|
|
; SSE41: # %bb.0:
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm1
|
|
|
|
; SSE41-NEXT: pxor %xmm0, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrd $0, %edi, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrd $0, %esi, %xmm1
|
|
|
|
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: PR41512:
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpinsrd $0, %edi, %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpinsrd $0, %esi, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
%ins1 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %x, i32 0
|
|
|
|
%ins2 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %y, i32 0
|
|
|
|
%r = shufflevector <4 x i32> %ins1, <4 x i32> %ins2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
|
|
|
ret <4 x i32> %r
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i64> @PR41512_v4i64(i64 %x, i64 %y) {
|
|
|
|
; SSE2-LABEL: PR41512_v4i64:
|
|
|
|
; SSE2: # %bb.0:
|
|
|
|
; SSE2-NEXT: movq %rdi, %xmm0
|
|
|
|
; SSE2-NEXT: movq %rsi, %xmm1
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: PR41512_v4i64:
|
|
|
|
; SSE3: # %bb.0:
|
|
|
|
; SSE3-NEXT: movq %rdi, %xmm0
|
|
|
|
; SSE3-NEXT: movq %rsi, %xmm1
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: PR41512_v4i64:
|
|
|
|
; SSSE3: # %bb.0:
|
|
|
|
; SSSE3-NEXT: movq %rdi, %xmm0
|
|
|
|
; SSSE3-NEXT: movq %rsi, %xmm1
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: PR41512_v4i64:
|
|
|
|
; SSE41: # %bb.0:
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm1
|
|
|
|
; SSE41-NEXT: pxor %xmm0, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrq $0, %rdi, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrq $0, %rsi, %xmm1
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX1-LABEL: PR41512_v4i64:
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
; AVX1-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm1
|
|
|
|
; AVX1-NEXT: vpinsrq $0, %rsi, %xmm0, %xmm0
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX2-LABEL: PR41512_v4i64:
|
|
|
|
; AVX2: # %bb.0:
|
|
|
|
; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm1
|
|
|
|
; AVX2-NEXT: vpinsrq $0, %rsi, %xmm0, %xmm0
|
|
|
|
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
%ins1 = insertelement <4 x i64> <i64 undef, i64 0, i64 undef, i64 undef>, i64 %x, i32 0
|
|
|
|
%ins2 = insertelement <4 x i64> <i64 undef, i64 0, i64 undef, i64 undef>, i64 %y, i32 0
|
|
|
|
%r = shufflevector <4 x i64> %ins1, <4 x i64> %ins2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
|
|
|
ret <4 x i64> %r
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x float> @PR41512_v8f32(float %x, float %y) {
|
|
|
|
; SSE2-LABEL: PR41512_v8f32:
|
|
|
|
; SSE2: # %bb.0:
|
|
|
|
; SSE2-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE2-NEXT: xorps %xmm3, %xmm3
|
|
|
|
; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
|
|
|
|
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
|
|
|
|
; SSE2-NEXT: movaps %xmm3, %xmm0
|
|
|
|
; SSE2-NEXT: movaps %xmm2, %xmm1
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: PR41512_v8f32:
|
|
|
|
; SSE3: # %bb.0:
|
|
|
|
; SSE3-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE3-NEXT: xorps %xmm3, %xmm3
|
|
|
|
; SSE3-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
|
|
|
|
; SSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
|
|
|
|
; SSE3-NEXT: movaps %xmm3, %xmm0
|
|
|
|
; SSE3-NEXT: movaps %xmm2, %xmm1
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: PR41512_v8f32:
|
|
|
|
; SSSE3: # %bb.0:
|
|
|
|
; SSSE3-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSSE3-NEXT: xorps %xmm3, %xmm3
|
|
|
|
; SSSE3-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
|
|
|
|
; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
|
|
|
|
; SSSE3-NEXT: movaps %xmm3, %xmm0
|
|
|
|
; SSSE3-NEXT: movaps %xmm2, %xmm1
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: PR41512_v8f32:
|
|
|
|
; SSE41: # %bb.0:
|
|
|
|
; SSE41-NEXT: xorps %xmm2, %xmm2
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
|
|
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: PR41512_v8f32:
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
; AVX-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
|
|
|
|
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
|
|
|
|
; AVX-NEXT: vxorps %xmm2, %xmm2, %xmm2
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
|
|
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
|
|
|
|
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
%ins1 = insertelement <8 x float> zeroinitializer, float %x, i32 0
|
|
|
|
%ins2 = insertelement <8 x float> zeroinitializer, float %y, i32 0
|
|
|
|
%r = shufflevector <8 x float> %ins1, <8 x float> %ins2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
|
|
|
|
ret <8 x float> %r
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x i32> @PR41512_loads(i32* %p1, i32* %p2) {
|
|
|
|
; SSE2-LABEL: PR41512_loads:
|
|
|
|
; SSE2: # %bb.0:
|
|
|
|
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE3-LABEL: PR41512_loads:
|
|
|
|
; SSE3: # %bb.0:
|
|
|
|
; SSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; SSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
; SSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSSE3-LABEL: PR41512_loads:
|
|
|
|
; SSSE3: # %bb.0:
|
|
|
|
; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
; SSSE3-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
;
|
|
|
|
; SSE41-LABEL: PR41512_loads:
|
|
|
|
; SSE41: # %bb.0:
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm1
|
|
|
|
; SSE41-NEXT: pxor %xmm0, %xmm0
|
|
|
|
; SSE41-NEXT: pinsrd $0, (%rdi), %xmm0
|
|
|
|
; SSE41-NEXT: pinsrd $0, (%rsi), %xmm1
|
|
|
|
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
; SSE41-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: PR41512_loads:
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpinsrd $0, (%rdi), %xmm0, %xmm1
|
|
|
|
; AVX-NEXT: vpinsrd $0, (%rsi), %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
%x = load i32, i32* %p1
|
|
|
|
%y = load i32, i32* %p2
|
|
|
|
%ins1 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %x, i32 0
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%ins2 = insertelement <4 x i32> <i32 undef, i32 0, i32 undef, i32 undef>, i32 %y, i32 0
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%r = shufflevector <4 x i32> %ins1, <4 x i32> %ins2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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ret <4 x i32> %r
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}
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