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llvm-project/llvm/test/CodeGen/X86/vec_set-D.ll

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[X86][SSE] Regenerated the vec_set tests. Replaced lots of dodgy greps with actual codegen llvm-svn: 265163
2016-04-02 01:40:25 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. llvm-svn: 50838
2008-05-08 08:57:18 +08:00
define <4 x i32> @t(i32 %x, i32 %y) nounwind {
[X86][SSE] Regenerated the vec_set tests. Replaced lots of dodgy greps with actual codegen llvm-svn: 265163
2016-04-02 01:40:25 +08:00
; CHECK-LABEL: t:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86][SSE] Fix domains for VZEXT_LOAD type instructions Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions. Differential Revision: https://reviews.llvm.org/D27684 llvm-svn: 289825
2016-12-16 00:05:29 +08:00
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
[X86][SSE] Regenerated the vec_set tests. Replaced lots of dodgy greps with actual codegen llvm-svn: 265163
2016-04-02 01:40:25 +08:00
; CHECK-NEXT: retl
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
%tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
ret <4 x i32> %tmp2
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. llvm-svn: 50838
2008-05-08 08:57:18 +08:00
}