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llvm-project/llvm/test/CodeGen/X86/adx-intrinsics.ll

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[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=NOADX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=broadwell --show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=ADX
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM. llvm-svn: 216162
2014-08-21 17:27:00 +08:00
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
declare { i8, i32 } @llvm.x86.addcarryx.u32(i8, i32, i32)
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM. llvm-svn: 216162
2014-08-21 17:27:00 +08:00
define i8 @test_addcarryx_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: test_addcarryx_u32:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
%3 = extractvalue { i8, i32 } %ret, 0
ret i8 %3
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM. llvm-svn: 216162
2014-08-21 17:27:00 +08:00
}
[X86] Add load folding test cases for the addcarryx intrinsic. We are currently only able to fold a load in operand 1 to ADCX. A load in operand 0 will use the legacy ADC instruction. Ultimately I want to remove isel support for ADCX, but first I'm going to fix the shortcomings I know of so I can write proper MIR tests to maintain coverage later. llvm-svn: 341744
2018-09-08 14:31:41 +08:00
define i8 @test_addcarryx_u32_load(i8 %c, i32* %aptr, i32 %b, i8* %ptr) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: test_addcarryx_u32_load:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl (%rsi), %edx ## encoding: [0x13,0x16]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movl %edx, (%rcx) ## encoding: [0x89,0x11]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Add load folding test cases for the addcarryx intrinsic. We are currently only able to fold a load in operand 1 to ADCX. A load in operand 0 will use the legacy ADC instruction. Ultimately I want to remove isel support for ADCX, but first I'm going to fix the shortcomings I know of so I can write proper MIR tests to maintain coverage later. llvm-svn: 341744
2018-09-08 14:31:41 +08:00
%a = load i32, i32* %aptr
%ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
%3 = extractvalue { i8, i32 } %ret, 0
ret i8 %3
}
define i8 @test_addcarryx_u32_load2(i8 %c, i32 %a, i32* %bptr, i8* %ptr) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: test_addcarryx_u32_load2:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl (%rdx), %esi ## encoding: [0x13,0x32]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Add load folding test cases for the addcarryx intrinsic. We are currently only able to fold a load in operand 1 to ADCX. A load in operand 0 will use the legacy ADC instruction. Ultimately I want to remove isel support for ADCX, but first I'm going to fix the shortcomings I know of so I can write proper MIR tests to maintain coverage later. llvm-svn: 341744
2018-09-08 14:31:41 +08:00
%b = load i32, i32* %bptr
%ret = call { i8, i32 } @llvm.x86.addcarryx.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
%3 = extractvalue { i8, i32 } %ret, 0
ret i8 %3
}
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
declare { i8, i64 } @llvm.x86.addcarryx.u64(i8, i64, i64)
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM. llvm-svn: 216162
2014-08-21 17:27:00 +08:00
define i8 @test_addcarryx_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: test_addcarryx_u64:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%ret = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
store i64 %1, i64* %2, align 1
%3 = extractvalue { i8, i64 } %ret, 0
ret i8 %3
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM. llvm-svn: 216162
2014-08-21 17:27:00 +08:00
}
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
declare { i8, i32 } @llvm.x86.addcarry.u32(i8, i32, i32)
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
define i8 @test_addcarry_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: test_addcarry_u32:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcl %edx, %esi ## encoding: [0x11,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%ret = call { i8, i32 } @llvm.x86.addcarry.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
%3 = extractvalue { i8, i32 } %ret, 0
ret i8 %3
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
}
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
declare { i8, i64 } @llvm.x86.addcarry.u64(i8, i64, i64)
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
define i8 @test_addcarry_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: test_addcarry_u64:
; CHECK: ## %bb.0:
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: adcq %rdx, %rsi ## encoding: [0x48,0x11,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%ret = call { i8, i64 } @llvm.x86.addcarry.u64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
store i64 %1, i64* %2, align 1
%3 = extractvalue { i8, i64 } %ret, 0
ret i8 %3
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
}
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
declare { i8, i32 } @llvm.x86.subborrow.u32(i8, i32, i32)
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
define i8 @test_subborrow_u32(i8 %c, i32 %a, i32 %b, i8* %ptr) {
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-LABEL: test_subborrow_u32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: sbbl %edx, %esi ## encoding: [0x19,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
; CHECK-NEXT: movl %esi, (%rcx) ## encoding: [0x89,0x31]
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%ret = call { i8, i32 } @llvm.x86.subborrow.u32(i8 %c, i32 %a, i32 %b)
%1 = extractvalue { i8, i32 } %ret, 1
%2 = bitcast i8* %ptr to i32*
store i32 %1, i32* %2, align 1
%3 = extractvalue { i8, i32 } %ret, 0
ret i8 %3
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
}
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
declare { i8, i64 } @llvm.x86.subborrow.u64(i8, i64, i64)
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
define i8 @test_subborrow_u64(i8 %c, i64 %a, i64 %b, i8* %ptr) {
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-LABEL: test_subborrow_u64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-NEXT: addb $-1, %dil ## encoding: [0x40,0x80,0xc7,0xff]
; CHECK-NEXT: sbbq %rdx, %rsi ## encoding: [0x48,0x19,0xd6]
; CHECK-NEXT: setb %al ## encoding: [0x0f,0x92,0xc0]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
; CHECK-NEXT: movq %rsi, (%rcx) ## encoding: [0x48,0x89,0x31]
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%ret = call { i8, i64 } @llvm.x86.subborrow.u64(i8 %c, i64 %a, i64 %b)
%1 = extractvalue { i8, i64 } %ret, 1
%2 = bitcast i8* %ptr to i64*
store i64 %1, i64* %2, align 1
%3 = extractvalue { i8, i64 } %ret, 0
ret i8 %3
[x86] Added _addcarry_ and _subborrow_ intrinsics llvm-svn: 216164
2014-08-21 17:43:43 +08:00
}
[X86] When handling addcarry intrinsic, create the flag result with the correct type so we don't crash if we use a memory instruction Summary: Previously we were creating the flag result with MVT::Other which is interpretted as a Chain node. If we used a memory form of the instruction we would end up with a copyToReg that consumed the chain result of the adcx instruction instead of the flag result. Pretty sure we should be using MVT::i32 here, that's what we do other places we create these node types. We should probably consider this for 5.0 as well. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36645 llvm-svn: 310784
2017-08-13 04:19:44 +08:00
; Try a version with loads. Previously we crashed on this.
define i32 @load_crash(i64* nocapture readonly %a, i64* nocapture readonly %b, i64* %res) {
[X86] Remove isel patterns for ADCX instruction There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
2018-09-12 23:47:34 +08:00
; CHECK-LABEL: load_crash:
; CHECK: ## %bb.0:
; CHECK-NEXT: movq (%rdi), %rax ## encoding: [0x48,0x8b,0x07]
; CHECK-NEXT: xorl %ecx, %ecx ## encoding: [0x31,0xc9]
; CHECK-NEXT: addb $-1, %cl ## encoding: [0x80,0xc1,0xff]
; CHECK-NEXT: adcq (%rsi), %rax ## encoding: [0x48,0x13,0x06]
; CHECK-NEXT: setb %cl ## encoding: [0x0f,0x92,0xc1]
; CHECK-NEXT: movq %rax, (%rdx) ## encoding: [0x48,0x89,0x02]
; CHECK-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] When handling addcarry intrinsic, create the flag result with the correct type so we don't crash if we use a memory instruction Summary: Previously we were creating the flag result with MVT::Other which is interpretted as a Chain node. If we used a memory form of the instruction we would end up with a copyToReg that consumed the chain result of the adcx instruction instead of the flag result. Pretty sure we should be using MVT::i32 here, that's what we do other places we create these node types. We should probably consider this for 5.0 as well. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36645 llvm-svn: 310784
2017-08-13 04:19:44 +08:00
%1 = load i64, i64* %a, align 8
%2 = load i64, i64* %b, align 8
%3 = bitcast i64* %res to i8*
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%4 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 0, i64 %1, i64 %2)
%5 = extractvalue { i8, i64 } %4, 1
%6 = bitcast i8* %3 to i64*
store i64 %5, i64* %6, align 1
%7 = extractvalue { i8, i64 } %4, 0
%conv = zext i8 %7 to i32
[X86] When handling addcarry intrinsic, create the flag result with the correct type so we don't crash if we use a memory instruction Summary: Previously we were creating the flag result with MVT::Other which is interpretted as a Chain node. If we used a memory form of the instruction we would end up with a copyToReg that consumed the chain result of the adcx instruction instead of the flag result. Pretty sure we should be using MVT::i32 here, that's what we do other places we create these node types. We should probably consider this for 5.0 as well. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36645 llvm-svn: 310784
2017-08-13 04:19:44 +08:00
ret i32 %conv
}
; Try a really simple all zero input case, which also used to crash
define void @allzeros() {
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-LABEL: allzeros:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0: ## %entry
[X86][ADX] Regenerate ADX intrinsics tests llvm-svn: 311198
2017-08-19 05:21:14 +08:00
; CHECK-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
; CHECK-NEXT: addb $-1, %al ## encoding: [0x04,0xff]
; CHECK-NEXT: sbbq %rax, %rax ## encoding: [0x48,0x19,0xc0]
; CHECK-NEXT: andl $1, %eax ## encoding: [0x83,0xe0,0x01]
; CHECK-NEXT: movq %rax, 0 ## encoding: [0x48,0x89,0x04,0x25,0x00,0x00,0x00,0x00]
; CHECK-NEXT: retq ## encoding: [0xc3]
[X86] When handling addcarry intrinsic, create the flag result with the correct type so we don't crash if we use a memory instruction Summary: Previously we were creating the flag result with MVT::Other which is interpretted as a Chain node. If we used a memory form of the instruction we would end up with a copyToReg that consumed the chain result of the adcx instruction instead of the flag result. Pretty sure we should be using MVT::i32 here, that's what we do other places we create these node types. We should probably consider this for 5.0 as well. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36645 llvm-svn: 310784
2017-08-13 04:19:44 +08:00
entry:
[X86] Change the addcarry and subborrow intrinsics to return 2 results and remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
2018-09-08 00:58:39 +08:00
%0 = call { i8, i64 } @llvm.x86.addcarryx.u64(i8 0, i64 0, i64 0)
%1 = extractvalue { i8, i64 } %0, 1
store i64 %1, i64* null, align 1
%2 = extractvalue { i8, i64 } %0, 0
[X86] When handling addcarry intrinsic, create the flag result with the correct type so we don't crash if we use a memory instruction Summary: Previously we were creating the flag result with MVT::Other which is interpretted as a Chain node. If we used a memory form of the instruction we would end up with a copyToReg that consumed the chain result of the adcx instruction instead of the flag result. Pretty sure we should be using MVT::i32 here, that's what we do other places we create these node types. We should probably consider this for 5.0 as well. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36645 llvm-svn: 310784
2017-08-13 04:19:44 +08:00
ret void
}