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llvm-project/llvm/test/CodeGen/AArch64/arm64-fp.ll

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[AArch64][x86] add tests for possible infinite loops in DAGCombiner; NFC This is a reduction of a test that failed (infinite looped) with rGd1f0bdf2d2df (subsequently reverted). I've duplicated it for 2 targets to increase coverage - everything down here is wobbly.
2019-12-12 08:38:37 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[AARCH64] Enable AARCH64 lit tests on windows dev machines As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
2016-07-19 21:35:11 +08:00
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
define float @t1(i1 %a, float %b, float %c) nounwind {
[AArch64][x86] add tests for possible infinite loops in DAGCombiner; NFC This is a reduction of a test that failed (infinite looped) with rGd1f0bdf2d2df (subsequently reverted). I've duplicated it for 2 targets to increase coverage - everything down here is wobbly.
2019-12-12 08:38:37 +08:00
; CHECK-LABEL: t1:
; CHECK: // %bb.0:
; CHECK-NEXT: tst w0, #0x1
; CHECK-NEXT: fcsel s0, s0, s1, ne
; CHECK-NEXT: ret
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
%sel = select i1 %a, float %b, float %c
ret float %sel
}
[AArch64][x86] add tests for possible infinite loops in DAGCombiner; NFC This is a reduction of a test that failed (infinite looped) with rGd1f0bdf2d2df (subsequently reverted). I've duplicated it for 2 targets to increase coverage - everything down here is wobbly.
2019-12-12 08:38:37 +08:00
; This may infinite loop if isNegatibleForFree and getNegatedExpression are conflicted.
define double @negation_propagation(double* %arg, double %arg1, double %arg2) {
; CHECK-LABEL: negation_propagation:
; CHECK: // %bb.0:
; CHECK-NEXT: fmov d2, #1.00000000
; CHECK-NEXT: fdiv d0, d2, d0
; CHECK-NEXT: fmul d2, d0, d0
; CHECK-NEXT: fmul d1, d0, d1
; CHECK-NEXT: fmul d0, d0, d2
; CHECK-NEXT: fsub d0, d1, d0
; CHECK-NEXT: ret
%t = fdiv double 1.0, %arg1
%t7 = fmul double %t, %arg2
%t10 = fneg double %t7
%t11 = fmul double %t, %t
%t13 = fsub double %t11, %t
%t14 = fneg double %t
%t15 = fmul double %t, %t14
%t16 = fmul double %t, %t15
%t18 = fadd double %t16, %t7
ret double %t18
}
[AArch64] add test for fsub+fneg; NFC D72015 proposes to restrict the current behavior.
2019-12-31 23:25:41 +08:00
define { double, double } @testfn(double %x, double %y) #0 {
; CHECK-LABEL: testfn:
; CHECK: // %bb.0:
DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz This was increasing the number of instructions when fsub was legalized on AMDGPU with no signed zeros enabled. This fold should be guarded by hasOneUse, and I don't think getNode should be doing that. The same fold is already done as a regular combine through isNegatibleForFree. This does require duplicating, even though isNegatibleForFree does this combine already (and properly checks hasOneUse) to avoid one PPC regression. In the regression, the outer fneg has nsz but the fsub operand does not. isNegatibleForFree only sees the operand, and doesn't see it's used from a nsz context. A nsz parameter needs to be added and threaded through isNegatibleForFree to avoid this.
2019-12-31 03:46:24 +08:00
; CHECK-NEXT: fsub d0, d0, d1
; CHECK-NEXT: fneg d1, d0
[AArch64] add test for fsub+fneg; NFC D72015 proposes to restrict the current behavior.
2019-12-31 23:25:41 +08:00
; CHECK-NEXT: ret
%sub = fsub fast double %x, %y
%neg = fneg fast double %sub
%r0 = insertvalue { double, double } undef, double %sub, 0
%r1 = insertvalue { double, double } %r0, double %neg, 1
ret { double, double } %r1
}
attributes #0 = { "no-signed-zeros-fp-math"="true" }