forked from OSchip/llvm-project
113 lines
3.1 KiB
LLVM
113 lines
3.1 KiB
LLVM
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; RUN: opt < %s -inline -S | FileCheck %s
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; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s
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; Test that bar and bar2 are both inlined throughout and removed.
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@A = weak global i32 0 ; <i32*> [#uses=1]
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@B = weak global i32 0 ; <i32*> [#uses=1]
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@C = weak global i32 0 ; <i32*> [#uses=1]
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define fastcc void @foo(i32 %X) {
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entry:
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; CHECK-LABEL: @foo(
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%ALL = alloca i32, align 4 ; <i32*> [#uses=1]
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%tmp1 = and i32 %X, 1 ; <i32> [#uses=1]
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%tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp1.upgrd.1, label %cond_next, label %cond_true
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cond_true: ; preds = %entry
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store i32 1, i32* @A
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br label %cond_next
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cond_next: ; preds = %cond_true, %entry
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%tmp4 = and i32 %X, 2 ; <i32> [#uses=1]
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%tmp4.upgrd.2 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1]
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br i1 %tmp4.upgrd.2, label %cond_next7, label %cond_true5
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cond_true5: ; preds = %cond_next
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store i32 1, i32* @B
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br label %cond_next7
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cond_next7: ; preds = %cond_true5, %cond_next
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%tmp10 = and i32 %X, 4 ; <i32> [#uses=1]
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%tmp10.upgrd.3 = icmp eq i32 %tmp10, 0 ; <i1> [#uses=1]
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br i1 %tmp10.upgrd.3, label %cond_next13, label %cond_true11
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cond_true11: ; preds = %cond_next7
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store i32 1, i32* @C
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br label %cond_next13
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cond_next13: ; preds = %cond_true11, %cond_next7
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%tmp16 = and i32 %X, 8 ; <i32> [#uses=1]
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%tmp16.upgrd.4 = icmp eq i32 %tmp16, 0 ; <i1> [#uses=1]
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br i1 %tmp16.upgrd.4, label %UnifiedReturnBlock, label %cond_true17
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cond_true17: ; preds = %cond_next13
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call void @ext( i32* %ALL )
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ret void
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UnifiedReturnBlock: ; preds = %cond_next13
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ret void
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}
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; CHECK-NOT: @bar(
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define internal fastcc void @bar(i32 %X) {
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entry:
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%ALL = alloca i32, align 4 ; <i32*> [#uses=1]
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%tmp1 = and i32 %X, 1 ; <i32> [#uses=1]
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%tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp1.upgrd.1, label %cond_next, label %cond_true
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cond_true: ; preds = %entry
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store i32 1, i32* @A
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br label %cond_next
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cond_next: ; preds = %cond_true, %entry
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%tmp4 = and i32 %X, 2 ; <i32> [#uses=1]
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%tmp4.upgrd.2 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1]
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br i1 %tmp4.upgrd.2, label %cond_next7, label %cond_true5
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cond_true5: ; preds = %cond_next
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store i32 1, i32* @B
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br label %cond_next7
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cond_next7: ; preds = %cond_true5, %cond_next
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%tmp10 = and i32 %X, 4 ; <i32> [#uses=1]
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%tmp10.upgrd.3 = icmp eq i32 %tmp10, 0 ; <i1> [#uses=1]
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br i1 %tmp10.upgrd.3, label %cond_next13, label %cond_true11
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cond_true11: ; preds = %cond_next7
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store i32 1, i32* @C
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br label %cond_next13
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cond_next13: ; preds = %cond_true11, %cond_next7
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%tmp16 = and i32 %X, 8 ; <i32> [#uses=1]
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%tmp16.upgrd.4 = icmp eq i32 %tmp16, 0 ; <i1> [#uses=1]
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br i1 %tmp16.upgrd.4, label %UnifiedReturnBlock, label %cond_true17
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cond_true17: ; preds = %cond_next13
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call void @foo( i32 %X )
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ret void
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UnifiedReturnBlock: ; preds = %cond_next13
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ret void
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}
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define internal fastcc void @bar2(i32 %X) {
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entry:
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call void @foo( i32 %X )
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ret void
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}
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declare void @ext(i32*)
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define void @test(i32 %X) {
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entry:
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; CHECK: test
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; CHECK-NOT: @bar(
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tail call fastcc void @bar( i32 %X )
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tail call fastcc void @bar( i32 %X )
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tail call fastcc void @bar2( i32 %X )
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tail call fastcc void @bar2( i32 %X )
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ret void
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; CHECK: ret
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}
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