forked from OSchip/llvm-project
257 lines
10 KiB
Python
257 lines
10 KiB
Python
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""" This module implement Dwarf expression opcode parser. """
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import lldb
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# DWARF Expression operators.
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DW_OP_addr = 0x03
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DW_OP_deref = 0x06
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DW_OP_const1u = 0x08
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DW_OP_const1s = 0x09
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DW_OP_const2u = 0x0A
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DW_OP_const2s = 0x0B
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DW_OP_const4u = 0x0C
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DW_OP_const4s = 0x0D
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DW_OP_const8u = 0x0E
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DW_OP_const8s = 0x0F
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DW_OP_constu = 0x10
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DW_OP_consts = 0x11
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DW_OP_dup = 0x12
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DW_OP_drop = 0x13
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DW_OP_over = 0x14
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DW_OP_pick = 0x15
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DW_OP_swap = 0x16
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DW_OP_rot = 0x17
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DW_OP_xderef = 0x18
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DW_OP_abs = 0x19
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DW_OP_and = 0x1A
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DW_OP_div = 0x1B
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DW_OP_minus = 0x1C
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DW_OP_mod = 0x1D
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DW_OP_mul = 0x1E
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DW_OP_neg = 0x1F
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DW_OP_not = 0x20
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DW_OP_or = 0x21
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DW_OP_plus = 0x22
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DW_OP_plus_uconst = 0x23
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DW_OP_shl = 0x24
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DW_OP_shr = 0x25
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DW_OP_shra = 0x26
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DW_OP_xor = 0x27
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DW_OP_skip = 0x2F
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DW_OP_bra = 0x28
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DW_OP_eq = 0x29
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DW_OP_ge = 0x2A
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DW_OP_gt = 0x2B
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DW_OP_le = 0x2C
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DW_OP_lt = 0x2D
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DW_OP_ne = 0x2E
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DW_OP_lit0 = 0x30
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DW_OP_lit1 = 0x31
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DW_OP_lit2 = 0x32
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DW_OP_lit3 = 0x33
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DW_OP_lit4 = 0x34
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DW_OP_lit5 = 0x35
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DW_OP_lit6 = 0x36
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DW_OP_lit7 = 0x37
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DW_OP_lit8 = 0x38
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DW_OP_lit9 = 0x39
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DW_OP_lit10 = 0x3A
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DW_OP_lit11 = 0x3B
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DW_OP_lit12 = 0x3C
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DW_OP_lit13 = 0x3D
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DW_OP_lit14 = 0x3E
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DW_OP_lit15 = 0x3F
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DW_OP_lit16 = 0x40
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DW_OP_lit17 = 0x41
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DW_OP_lit18 = 0x42
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DW_OP_lit19 = 0x43
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DW_OP_lit20 = 0x44
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DW_OP_lit21 = 0x45
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DW_OP_lit22 = 0x46
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DW_OP_lit23 = 0x47
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DW_OP_lit24 = 0x48
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DW_OP_lit25 = 0x49
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DW_OP_lit26 = 0x4A
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DW_OP_lit27 = 0x4B
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DW_OP_lit28 = 0x4C
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DW_OP_lit29 = 0x4D
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DW_OP_lit30 = 0x4E
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DW_OP_lit31 = 0x4F
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DW_OP_reg0 = 0x50
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DW_OP_reg1 = 0x51
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DW_OP_reg2 = 0x52
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DW_OP_reg3 = 0x53
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DW_OP_reg4 = 0x54
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DW_OP_reg5 = 0x55
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DW_OP_reg6 = 0x56
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DW_OP_reg7 = 0x57
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DW_OP_reg8 = 0x58
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DW_OP_reg9 = 0x59
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DW_OP_reg10 = 0x5A
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DW_OP_reg11 = 0x5B
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DW_OP_reg12 = 0x5C
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DW_OP_reg13 = 0x5D
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DW_OP_reg14 = 0x5E
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DW_OP_reg15 = 0x5F
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DW_OP_reg16 = 0x60
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DW_OP_reg17 = 0x61
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DW_OP_reg18 = 0x62
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DW_OP_reg19 = 0x63
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DW_OP_reg20 = 0x64
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DW_OP_reg21 = 0x65
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DW_OP_reg22 = 0x66
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DW_OP_reg23 = 0x67
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DW_OP_reg24 = 0x68
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DW_OP_reg25 = 0x69
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DW_OP_reg26 = 0x6A
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DW_OP_reg27 = 0x6B
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DW_OP_reg28 = 0x6C
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DW_OP_reg29 = 0x6D
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DW_OP_reg30 = 0x6E
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DW_OP_reg31 = 0x6F
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DW_OP_breg0 = 0x70
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DW_OP_breg1 = 0x71
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DW_OP_breg2 = 0x72
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DW_OP_breg3 = 0x73
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DW_OP_breg4 = 0x74
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DW_OP_breg5 = 0x75
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DW_OP_breg6 = 0x76
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DW_OP_breg7 = 0x77
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DW_OP_breg8 = 0x78
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DW_OP_breg9 = 0x79
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DW_OP_breg10 = 0x7A
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DW_OP_breg11 = 0x7B
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DW_OP_breg12 = 0x7C
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DW_OP_breg13 = 0x7D
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DW_OP_breg14 = 0x7E
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DW_OP_breg15 = 0x7F
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DW_OP_breg16 = 0x80
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DW_OP_breg17 = 0x81
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DW_OP_breg18 = 0x82
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DW_OP_breg19 = 0x83
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DW_OP_breg20 = 0x84
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DW_OP_breg21 = 0x85
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DW_OP_breg22 = 0x86
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DW_OP_breg23 = 0x87
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DW_OP_breg24 = 0x88
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DW_OP_breg25 = 0x89
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DW_OP_breg26 = 0x8A
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DW_OP_breg27 = 0x8B
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DW_OP_breg28 = 0x8C
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DW_OP_breg29 = 0x8D
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DW_OP_breg30 = 0x8E
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DW_OP_breg31 = 0x8F
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DW_OP_regx = 0x90
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DW_OP_fbreg = 0x91
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DW_OP_bregx = 0x92
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DW_OP_piece = 0x93
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DW_OP_deref_size = 0x94
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DW_OP_xderef_size = 0x95
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DW_OP_nop = 0x96
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DW_OP_push_object_address = 0x97
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DW_OP_call2 = 0x98
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DW_OP_call4 = 0x99
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DW_OP_call_ref = 0x9A
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DW_OP_form_tls_address = 0x9B
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DW_OP_call_frame_cfa = 0x9C
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DW_OP_bit_piece = 0x9D
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DW_OP_implicit_value = 0x9E
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DW_OP_stack_value = 0x9F
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DW_OP_lo_user = 0xE0
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DW_OP_GNU_push_tls_address = 0xE0
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DW_OP_APPLE_uninit = 0xF0
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DW_OP_hi_user = 0xFF
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class DwarfOpcodeParser(object):
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def updateRegInfoBitsize(self, reg_info, byte_order):
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""" Update the regInfo bit size. """
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# Evaluate Dwarf Expression
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expr_result = self.evaluateDwarfExpression(reg_info["dynamic_size_dwarf_expr_bytes"],
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byte_order)
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if expr_result == 0:
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reg_info["bitsize"] = 32
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elif expr_result == 1:
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reg_info["bitsize"] = 64
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def evaluateDwarfExpression(self, dwarf_opcode, byte_order):
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"""Evaluate Dwarf Expression. """
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dwarf_opcode = [dwarf_opcode[i:i+2] for i in range(0,len(dwarf_opcode),2)]
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dwarf_data = []
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for index in range(len(dwarf_opcode)):
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if index < len(dwarf_opcode):
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val = int(dwarf_opcode[index], 16)
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else:
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break
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if val == DW_OP_regx:
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# Read register number
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self.assertTrue(len(dwarf_opcode) > (index + 1))
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reg_no = int(dwarf_opcode.pop(index + 1), 16)
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self.reset_test_sequence()
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# Read register value
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self.test_sequence.add_log_lines(
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["read packet: $p{0:x}#00".format(reg_no),
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{"direction": "send", "regex": r"^\$([0-9a-fA-F]+)#",
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"capture": {1: "p_response"}}],True)
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Context = self.expect_gdbremote_sequence()
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self.assertIsNotNone(Context)
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p_response = Context.get("p_response")
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self.assertIsNotNone(p_response)
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if byte_order == lldb.eByteOrderLittle:
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# In case of little endian
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# first decode the HEX ASCII bytes and then reverse it
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# to get actual value of SR register
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p_response = "".join(reversed([p_response[i:i+2] for i in range(0,
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len(p_response),2)]))
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# Push register value
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dwarf_data.append(int(p_response,16))
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elif val == DW_OP_lit1:
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# Push literal 1
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dwarf_data.append(1)
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elif val == DW_OP_lit26:
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# Push literal 26
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dwarf_data.append(26)
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elif val == DW_OP_shl:
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# left shift and push the result back
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self.assertTrue(len(dwarf_data) > 1)
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shift_amount = dwarf_data.pop()
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val_to_shift = dwarf_data.pop()
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result = val_to_shift << shift_amount
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dwarf_data.append(result)
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elif val == DW_OP_shr:
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# Right shift and push the result back
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self.assertTrue(len(dwarf_data) > 1)
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shift_amount = dwarf_data.pop()
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val_to_shift = dwarf_data.pop()
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result = val_to_shift >> shift_amount
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dwarf_data.append(result)
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elif val == DW_OP_and:
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# And of topmost 2 elements and push the result back
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first_ele = dwarf_data.pop()
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second_ele = dwarf_data.pop()
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result = first_ele & second_ele
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dwarf_data.append(result)
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else:
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self.assertTrue(False and "Unprocess Dwarf Opcode")
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self.assertTrue(len(dwarf_data) == 1)
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expr_result = dwarf_data.pop()
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return expr_result
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