2018-05-19 03:30:49 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=ANY,STRICT
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -enable-unsafe-fp-math | FileCheck %s --check-prefixes=ANY,UNSAFE
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2018-05-19 06:31:43 +08:00
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define float @fadd_zero(float %x) {
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; STRICT-LABEL: fadd_zero:
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; STRICT: # %bb.0:
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; STRICT-NEXT: xorps %xmm1, %xmm1
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; STRICT-NEXT: addss %xmm1, %xmm0
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; STRICT-NEXT: retq
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;
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; UNSAFE-LABEL: fadd_zero:
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; UNSAFE: # %bb.0:
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; UNSAFE-NEXT: retq
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%r = fadd float %x, 0.0
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ret float %r
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}
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define float @fadd_negzero(float %x) {
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2018-06-19 07:44:59 +08:00
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; ANY-LABEL: fadd_negzero:
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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2018-05-19 06:31:43 +08:00
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%r = fadd float %x, -0.0
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ret float %r
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}
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2018-05-19 03:30:49 +08:00
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2018-06-19 07:44:59 +08:00
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define float @fadd_produce_zero(float %x) {
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; ANY-LABEL: fadd_produce_zero:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps %xmm0, %xmm0
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; ANY-NEXT: retq
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%neg = fsub nsz float 0.0, %x
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%r = fadd nnan float %neg, %x
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ret float %r
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}
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define float @fadd_reassociate(float %x) {
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; ANY-LABEL: fadd_reassociate:
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; ANY: # %bb.0:
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; ANY-NEXT: addss {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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%sum = fadd float %x, 8.0
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%r = fadd reassoc nsz float %sum, 12.0
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ret float %r
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}
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2018-06-09 01:39:50 +08:00
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define float @fadd_negzero_nsz(float %x) {
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; ANY-LABEL: fadd_negzero_nsz:
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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%r = fadd nsz float %x, -0.0
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ret float %r
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}
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2018-05-19 06:31:43 +08:00
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define float @fadd_zero_nsz(float %x) {
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; ANY-LABEL: fadd_zero_nsz:
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2018-05-19 03:30:49 +08:00
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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%r = fadd nsz float %x, 0.0
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ret float %r
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}
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2018-06-09 01:39:50 +08:00
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define float @fsub_zero(float %x) {
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; ANY-LABEL: fsub_zero:
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2018-05-19 03:30:49 +08:00
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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2018-06-09 01:39:50 +08:00
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%r = fsub float %x, 0.0
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2018-05-19 03:30:49 +08:00
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ret float %r
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}
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2018-06-09 01:39:50 +08:00
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define float @fsub_self(float %x) {
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; ANY-LABEL: fsub_self:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps %xmm0, %xmm0
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; ANY-NEXT: retq
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2018-08-09 06:18:16 +08:00
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%r = fsub nnan float %x, %x
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2018-05-19 03:30:49 +08:00
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ret float %r
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}
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2018-06-15 02:48:31 +08:00
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define float @fsub_neg_x_y(float %x, float %y) {
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; ANY-LABEL: fsub_neg_x_y:
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; ANY: # %bb.0:
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; ANY-NEXT: subss %xmm0, %xmm1
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; ANY-NEXT: movaps %xmm1, %xmm0
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; ANY-NEXT: retq
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%neg = fsub nsz float 0.0, %x
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%r = fadd nsz float %neg, %y
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ret float %r
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}
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2018-08-08 06:52:57 +08:00
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define float @fsub_neg_y(float %x, float %y) {
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2018-08-10 01:00:03 +08:00
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; ANY-LABEL: fsub_neg_y:
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; ANY: # %bb.0:
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; ANY-NEXT: mulss {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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2018-08-09 07:06:59 +08:00
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%mul = fmul float %x, 5.0
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2018-08-09 06:18:16 +08:00
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%add = fadd float %mul, %y
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%r = fsub nsz reassoc float %y, %add
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ret float %r
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}
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2018-08-09 07:06:59 +08:00
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define float @fsub_neg_y_commute(float %x, float %y) {
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2018-08-10 01:00:03 +08:00
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; ANY-LABEL: fsub_neg_y_commute:
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; ANY: # %bb.0:
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; ANY-NEXT: mulss {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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2018-08-09 07:06:59 +08:00
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%mul = fmul float %x, 5.0
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%add = fadd float %y, %mul
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%r = fsub nsz reassoc float %y, %add
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ret float %r
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}
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2018-08-09 06:18:16 +08:00
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; Y - (X + Y) --> -X
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define float @fsub_fadd_common_op_fneg(float %x, float %y) {
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2018-08-10 01:00:03 +08:00
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; ANY-LABEL: fsub_fadd_common_op_fneg:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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2018-08-09 06:18:16 +08:00
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%a = fadd float %x, %y
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%r = fsub reassoc nsz float %y, %a
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ret float %r
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}
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; Y - (X + Y) --> -X
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define <4 x float> @fsub_fadd_common_op_fneg_vec(<4 x float> %x, <4 x float> %y) {
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2018-08-10 01:00:03 +08:00
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; ANY-LABEL: fsub_fadd_common_op_fneg_vec:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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2018-08-09 06:18:16 +08:00
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%a = fadd <4 x float> %x, %y
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%r = fsub nsz reassoc <4 x float> %y, %a
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ret <4 x float> %r
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}
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; Y - (Y + X) --> -X
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; Commute operands of the 'add'.
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define float @fsub_fadd_common_op_fneg_commute(float %x, float %y) {
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2018-08-10 01:00:03 +08:00
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; ANY-LABEL: fsub_fadd_common_op_fneg_commute:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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2018-08-09 06:18:16 +08:00
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%a = fadd float %y, %x
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%r = fsub reassoc nsz float %y, %a
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2018-08-08 06:52:57 +08:00
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ret float %r
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}
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2018-08-09 06:18:16 +08:00
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; Y - (Y + X) --> -X
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define <4 x float> @fsub_fadd_common_op_fneg_commute_vec(<4 x float> %x, <4 x float> %y) {
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2018-08-10 01:00:03 +08:00
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; ANY-LABEL: fsub_fadd_common_op_fneg_commute_vec:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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2018-08-09 06:18:16 +08:00
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%a = fadd <4 x float> %y, %x
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%r = fsub reassoc nsz <4 x float> %y, %a
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ret <4 x float> %r
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}
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2018-05-19 06:31:43 +08:00
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define float @fsub_negzero(float %x) {
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; STRICT-LABEL: fsub_negzero:
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; STRICT: # %bb.0:
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; STRICT-NEXT: xorps %xmm1, %xmm1
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; STRICT-NEXT: addss %xmm1, %xmm0
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; STRICT-NEXT: retq
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;
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; UNSAFE-LABEL: fsub_negzero:
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2018-05-19 03:30:49 +08:00
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; UNSAFE: # %bb.0:
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; UNSAFE-NEXT: retq
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%r = fsub float %x, -0.0
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ret float %r
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}
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2018-06-09 01:39:50 +08:00
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define float @fsub_zero_nsz_1(float %x) {
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; ANY-LABEL: fsub_zero_nsz_1:
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2018-05-19 06:31:43 +08:00
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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%r = fsub nsz float %x, 0.0
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ret float %r
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}
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2018-06-09 01:39:50 +08:00
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define float @fsub_zero_nsz_2(float %x) {
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; ANY-LABEL: fsub_zero_nsz_2:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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%r = fsub nsz float 0.0, %x
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ret float %r
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}
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2018-05-19 06:31:43 +08:00
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define float @fsub_negzero_nsz(float %x) {
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; ANY-LABEL: fsub_negzero_nsz:
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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%r = fsub nsz float %x, -0.0
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ret float %r
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}
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2018-05-19 03:30:49 +08:00
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define float @fmul_zero(float %x) {
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2018-06-13 00:13:11 +08:00
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; ANY-LABEL: fmul_zero:
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; ANY: # %bb.0:
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; ANY-NEXT: xorps %xmm0, %xmm0
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; ANY-NEXT: retq
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2018-05-19 03:30:49 +08:00
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%r = fmul nnan nsz float %x, 0.0
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ret float %r
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}
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define float @fmul_one(float %x) {
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; ANY-LABEL: fmul_one:
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; ANY: # %bb.0:
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; ANY-NEXT: retq
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%r = fmul float %x, 1.0
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ret float %r
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}
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2018-06-13 00:13:11 +08:00
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define float @fmul_x_const_const(float %x) {
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; ANY-LABEL: fmul_x_const_const:
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; ANY: # %bb.0:
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; ANY-NEXT: mulss {{.*}}(%rip), %xmm0
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; ANY-NEXT: retq
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%mul = fmul reassoc float %x, 9.0
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%r = fmul reassoc float %mul, 4.0
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ret float %r
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}
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