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llvm-project/clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

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[AArch64][Driver][SVE] Allow -msve-vector-bits=<n>+ syntax to mean no maximum vscale This patch splits the existing SveVectorBits LangOpt into VScaleMin and VScaleMax LangOpts such that we can represent such an option. The cc1 option has also been split into -mvscale-{min,max}=<n> options so that the cc1 arguments better reflect the vscale_range IR attribute. Differential Revision: https://reviews.llvm.org/D111790
2021-10-14 19:04:33 +08:00
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -mvscale-min=4 -mvscale-max=4 -fallow-half-arguments-and-returns -Wconversion %s
[Sema][AArch64] Support arm_sve_vector_bits attribute This patch implements the semantics for the 'arm_sve_vector_bits' type attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1]. The purpose of this attribute is to define vector-length-specific (VLS) versions of existing vector-length-agnostic (VLA) types. The semantics were already implemented by D83551, although the implementation approach has since changed to represent VLSTs as VectorType in the AST and fixed-length vectors in the IR everywhere except in function args/returns. This is described in the prototype patch D85128 demonstrating the new approach. The semantic changes added in D83551 are changed since the AttributedType is replaced by VectorType in the AST. Minimal changes were necessary in the previous patch as the canonical type for both VLA and VLS was the same (i.e. sizeless), except in constructs such as globals and structs where sizeless types are unsupported. This patch reverts the changes that permitted VLS types that were represented as sizeless types in such circumstances, and adds support for implicit casting between VLA <-> VLS types as described in section 3.7.3.2 of the ACLE. Since the SVE builtin types for bool and uint8 are both represented as BuiltinType::UChar in VLSTs, two new vector kinds are implemented to distinguish predicate and data vectors. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D85736
2020-08-11 21:04:21 +08:00
// expected-no-diagnostics
[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors This patch adds support for implicit casting between GNU vectors and SVE vectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm C Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1]. This behavior makes it possible to use GNU vectors with ACLE functions that operate on VLAT. For example: typedef int8_t vec __attribute__((vector_size(32))); vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); } Tests are also added for implicit casting between GNU and fixed-length SVE vectors created by the 'arm_sve_vector_bits' attribute. This behavior makes it possible to use VLST with existing interfaces that operate on GNUT. For example: typedef int8_t vec1 __attribute__((vector_size(32))); void f(vec1); #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); void g(vec2 x) { f(x); } // OK #endif The `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicates interoperability with the GNU vector extension. This is the first patch providing support for this feature, which once complete will be enabled by the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` feature currently is. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D87607
2020-09-11 23:18:44 +08:00
#include <stdint.h>
[clang][aarch64] Drop experimental from __ARM_FEATURE_SVE_BITS macro The __ARM_FEATURE_SVE_BITS feature macro is specified in the Arm C Language Extensions (ACLE) for SVE [1] (version 00bet5). From the spec, where __ARM_FEATURE_SVE_BITS==N: When N is nonzero, indicates that the implementation is generating code for an N-bit SVE target and that the arm_sve_vector_bits(N) attribute is available. This was defined in D83550 as __ARM_FEATURE_SVE_BITS_EXPERIMENTAL and enabled under the -msve-vector-bits flag to simplify initial tests. This patch drops _EXPERIMENTAL now there is support for the feature. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D86720
2020-09-03 17:19:41 +08:00
#define N __ARM_FEATURE_SVE_BITS
[Sema][AArch64] Support arm_sve_vector_bits attribute This patch implements the semantics for the 'arm_sve_vector_bits' type attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1]. The purpose of this attribute is to define vector-length-specific (VLS) versions of existing vector-length-agnostic (VLA) types. The semantics were already implemented by D83551, although the implementation approach has since changed to represent VLSTs as VectorType in the AST and fixed-length vectors in the IR everywhere except in function args/returns. This is described in the prototype patch D85128 demonstrating the new approach. The semantic changes added in D83551 are changed since the AttributedType is replaced by VectorType in the AST. Minimal changes were necessary in the previous patch as the canonical type for both VLA and VLS was the same (i.e. sizeless), except in constructs such as globals and structs where sizeless types are unsupported. This patch reverts the changes that permitted VLS types that were represented as sizeless types in such circumstances, and adds support for implicit casting between VLA <-> VLS types as described in section 3.7.3.2 of the ACLE. Since the SVE builtin types for bool and uint8 are both represented as BuiltinType::UChar in VLSTs, two new vector kinds are implemented to distinguish predicate and data vectors. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D85736
2020-08-11 21:04:21 +08:00
typedef __SVInt8_t svint8_t;
typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors This patch adds support for implicit casting between GNU vectors and SVE vectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm C Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1]. This behavior makes it possible to use GNU vectors with ACLE functions that operate on VLAT. For example: typedef int8_t vec __attribute__((vector_size(32))); vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); } Tests are also added for implicit casting between GNU and fixed-length SVE vectors created by the 'arm_sve_vector_bits' attribute. This behavior makes it possible to use VLST with existing interfaces that operate on GNUT. For example: typedef int8_t vec1 __attribute__((vector_size(32))); void f(vec1); #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); void g(vec2 x) { f(x); } // OK #endif The `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicates interoperability with the GNU vector extension. This is the first patch providing support for this feature, which once complete will be enabled by the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` feature currently is. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D87607
2020-09-11 23:18:44 +08:00
typedef int8_t gnu_int8_t __attribute__((vector_size(N / 8)));
[Sema][AArch64] Support arm_sve_vector_bits attribute This patch implements the semantics for the 'arm_sve_vector_bits' type attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1]. The purpose of this attribute is to define vector-length-specific (VLS) versions of existing vector-length-agnostic (VLA) types. The semantics were already implemented by D83551, although the implementation approach has since changed to represent VLSTs as VectorType in the AST and fixed-length vectors in the IR everywhere except in function args/returns. This is described in the prototype patch D85128 demonstrating the new approach. The semantic changes added in D83551 are changed since the AttributedType is replaced by VectorType in the AST. Minimal changes were necessary in the previous patch as the canonical type for both VLA and VLS was the same (i.e. sizeless), except in constructs such as globals and structs where sizeless types are unsupported. This patch reverts the changes that permitted VLS types that were represented as sizeless types in such circumstances, and adds support for implicit casting between VLA <-> VLS types as described in section 3.7.3.2 of the ACLE. Since the SVE builtin types for bool and uint8 are both represented as BuiltinType::UChar in VLSTs, two new vector kinds are implemented to distinguish predicate and data vectors. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D85736
2020-08-11 21:04:21 +08:00
[AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversion According to https://godbolt.org/z/q5rME1naY and acle, we found that there are different SVE conversion behaviours between clang and gcc. It turns out that llvm does not handle SVE predicates width properly. This patch 1) checks SVE predicates width rightly with svbool_t type. 2) removes warning on svbool_t VLST <-> VLAT/GNUT conversion. 3) disables VLST <-> VLAT/GNUT conversion between SVE vectors and predicates due to different width. Differential Revision: https://reviews.llvm.org/D106333
2021-07-19 21:10:17 +08:00
typedef __SVBool_t svbool_t;
typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
typedef int8_t gnu_bool_t __attribute__((vector_size(N / 64)));
[Sema][AArch64] Support arm_sve_vector_bits attribute This patch implements the semantics for the 'arm_sve_vector_bits' type attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1]. The purpose of this attribute is to define vector-length-specific (VLS) versions of existing vector-length-agnostic (VLA) types. The semantics were already implemented by D83551, although the implementation approach has since changed to represent VLSTs as VectorType in the AST and fixed-length vectors in the IR everywhere except in function args/returns. This is described in the prototype patch D85128 demonstrating the new approach. The semantic changes added in D83551 are changed since the AttributedType is replaced by VectorType in the AST. Minimal changes were necessary in the previous patch as the canonical type for both VLA and VLS was the same (i.e. sizeless), except in constructs such as globals and structs where sizeless types are unsupported. This patch reverts the changes that permitted VLS types that were represented as sizeless types in such circumstances, and adds support for implicit casting between VLA <-> VLS types as described in section 3.7.3.2 of the ACLE. Since the SVE builtin types for bool and uint8 are both represented as BuiltinType::UChar in VLSTs, two new vector kinds are implemented to distinguish predicate and data vectors. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D85736
2020-08-11 21:04:21 +08:00
template<typename T> struct S { T var; };
S<fixed_int8_t> s;
[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors This patch adds support for implicit casting between GNU vectors and SVE vectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm C Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1]. This behavior makes it possible to use GNU vectors with ACLE functions that operate on VLAT. For example: typedef int8_t vec __attribute__((vector_size(32))); vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); } Tests are also added for implicit casting between GNU and fixed-length SVE vectors created by the 'arm_sve_vector_bits' attribute. This behavior makes it possible to use VLST with existing interfaces that operate on GNUT. For example: typedef int8_t vec1 __attribute__((vector_size(32))); void f(vec1); #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); void g(vec2 x) { f(x); } // OK #endif The `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicates interoperability with the GNU vector extension. This is the first patch providing support for this feature, which once complete will be enabled by the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` feature currently is. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D87607
2020-09-11 23:18:44 +08:00
// Test implicit casts between VLA and VLS vectors
[Sema][AArch64] Support arm_sve_vector_bits attribute This patch implements the semantics for the 'arm_sve_vector_bits' type attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1]. The purpose of this attribute is to define vector-length-specific (VLS) versions of existing vector-length-agnostic (VLA) types. The semantics were already implemented by D83551, although the implementation approach has since changed to represent VLSTs as VectorType in the AST and fixed-length vectors in the IR everywhere except in function args/returns. This is described in the prototype patch D85128 demonstrating the new approach. The semantic changes added in D83551 are changed since the AttributedType is replaced by VectorType in the AST. Minimal changes were necessary in the previous patch as the canonical type for both VLA and VLS was the same (i.e. sizeless), except in constructs such as globals and structs where sizeless types are unsupported. This patch reverts the changes that permitted VLS types that were represented as sizeless types in such circumstances, and adds support for implicit casting between VLA <-> VLS types as described in section 3.7.3.2 of the ACLE. Since the SVE builtin types for bool and uint8 are both represented as BuiltinType::UChar in VLSTs, two new vector kinds are implemented to distinguish predicate and data vectors. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D85736
2020-08-11 21:04:21 +08:00
svint8_t to_svint8_t(fixed_int8_t x) { return x; }
fixed_int8_t from_svint8_t(svint8_t x) { return x; }
[clang][aarch64] ACLE: Support implicit casts between GNU and SVE vectors This patch adds support for implicit casting between GNU vectors and SVE vectors when `__ARM_FEATURE_SVE_BITS==N`, as defined by the Arm C Language Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1]. This behavior makes it possible to use GNU vectors with ACLE functions that operate on VLAT. For example: typedef int8_t vec __attribute__((vector_size(32))); vec f(vec x) { return svasrd_x(svptrue_b8(), x, 1); } Tests are also added for implicit casting between GNU and fixed-length SVE vectors created by the 'arm_sve_vector_bits' attribute. This behavior makes it possible to use VLST with existing interfaces that operate on GNUT. For example: typedef int8_t vec1 __attribute__((vector_size(32))); void f(vec1); #if __ARM_FEATURE_SVE_BITS==256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(256))); void g(vec2 x) { f(x); } // OK #endif The `__ARM_FEATURE_SVE_VECTOR_OPERATORS` feature macro indicates interoperability with the GNU vector extension. This is the first patch providing support for this feature, which once complete will be enabled by the `-msve-vector-bits` flag, as the `__ARM_FEATURE_SVE_BITS` feature currently is. [1] https://developer.arm.com/documentation/100987/latest Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D87607
2020-09-11 23:18:44 +08:00
// Test implicit casts between GNU and VLA vectors
svint8_t to_svint8_t__from_gnu_int8_t(gnu_int8_t x) { return x; }
gnu_int8_t from_svint8_t__to_gnu_int8_t(svint8_t x) { return x; }
// Test implicit casts between GNU and VLS vectors
fixed_int8_t to_fixed_int8_t__from_gnu_int8_t(gnu_int8_t x) { return x; }
gnu_int8_t from_fixed_int8_t__to_gnu_int8_t(fixed_int8_t x) { return x; }
[AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversion According to https://godbolt.org/z/q5rME1naY and acle, we found that there are different SVE conversion behaviours between clang and gcc. It turns out that llvm does not handle SVE predicates width properly. This patch 1) checks SVE predicates width rightly with svbool_t type. 2) removes warning on svbool_t VLST <-> VLAT/GNUT conversion. 3) disables VLST <-> VLAT/GNUT conversion between SVE vectors and predicates due to different width. Differential Revision: https://reviews.llvm.org/D106333
2021-07-19 21:10:17 +08:00
// Test implicit casts between VLA and VLS predicates
svbool_t to_svbool_t(fixed_bool_t x) { return x; }
fixed_bool_t from_svbool_t(svbool_t x) { return x; }
// Test implicit casts between GNU and VLA predicates
svbool_t to_svbool_t__from_gnu_bool_t(gnu_bool_t x) { return x; }
gnu_bool_t from_svbool_t__to_gnu_bool_t(svbool_t x) { return x; }