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llvm-project/llvm/test/MC/ARM/neon-vst-encoding.s

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Add correct encodings for the basic form of vst1. llvm-svn: 118067
2010-11-03 05:06:06 +08:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. llvm-svn: 142583
2011-10-20 23:04:25 +08:00
vst1.8 {d16}, [r0, :64]
Enable some VST1 tests and add a few more. llvm-svn: 145443
2011-11-30 06:40:32 +08:00
vst1.16 {d16}, [r0]
vst1.32 {d16}, [r0]
vst1.64 {d16}, [r0]
vst1.8 {d16, d17}, [r0, :64]
vst1.16 {d16, d17}, [r0, :128]
vst1.32 {d16, d17}, [r0]
vst1.64 {d16, d17}, [r0]
vst1.8 {d16, d17, d18}, [r0, :64]
vst1.8 {d16, d17, d18}, [r0, :64]!
vst1.8 {d16, d17, d18}, [r0], r3
ARM assembly parsing and encoding for four-register VST1. llvm-svn: 145450
2011-11-30 06:58:48 +08:00
vst1.8 {d16, d17, d18, d19}, [r0, :64]
vst1.16 {d16, d17, d18, d19}, [r1, :64]!
vst1.64 {d16, d17, d18, d19}, [r3], r2
Add correct encodings for the basic form of vst1. llvm-svn: 118067
2010-11-03 05:06:06 +08:00
Tidy up formatting. llvm-svn: 142582
2011-10-20 22:57:47 +08:00
@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4]
Enable some VST1 tests and add a few more. llvm-svn: 145443
2011-11-30 06:40:32 +08:00
@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4]
@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4]
@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4]
@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4]
@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4]
ARM assembly parsing and encoding for four-register VST1. llvm-svn: 145450
2011-11-30 06:58:48 +08:00
@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4]
@ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. llvm-svn: 142583
2011-10-20 23:04:25 +08:00
ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
2011-12-15 03:35:22 +08:00
vst2.8 {d16, d17}, [r0, :64]
vst2.16 {d16, d17}, [r0, :128]
vst2.32 {d16, d17}, [r0]
vst2.8 {d16, d17, d18, d19}, [r0, :64]
vst2.16 {d16, d17, d18, d19}, [r0, :128]
vst2.32 {d16, d17, d18, d19}, [r0, :256]
ARM NEON fix alignment encoding for VST2 w/ writeback. Add tests for w/ writeback instruction parsing and encoding. llvm-svn: 146594
2011-12-15 05:49:24 +08:00
vst2.8 {d16, d17}, [r0, :64]!
vst2.16 {q15}, [r0, :128]!
vst2.32 {d14, d15}, [r0]!
vst2.8 {d16, d17, d18, d19}, [r0, :64]!
vst2.16 {d18-d21}, [r0, :128]!
vst2.32 {q4, q5}, [r0, :256]!
ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
2011-12-15 03:35:22 +08:00
@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4]
@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4]
@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4]
@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4]
@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4]
ARM NEON fix alignment encoding for VST2 w/ writeback. Add tests for w/ writeback instruction parsing and encoding. llvm-svn: 146594
2011-12-15 05:49:24 +08:00
@ CHECK: vst2.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x08,0x40,0xf4]
@ CHECK: vst2.16 {d30, d31}, [r0, :128]! @ encoding: [0x6d,0xe8,0x40,0xf4]
@ CHECK: vst2.32 {d14, d15}, [r0]! @ encoding: [0x8d,0xe8,0x00,0xf4]
@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]! @ encoding: [0x1d,0x03,0x40,0xf4]
@ CHECK: vst2.16 {d18, d19, d20, d21}, [r0, :128]! @ encoding: [0x6d,0x23,0x40,0xf4]
@ CHECK: vst2.32 {d8, d9, d10, d11}, [r0, :256]! @ encoding: [0xbd,0x83,0x00,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. llvm-svn: 142583
2011-10-20 23:04:25 +08:00
@ vst3.8 {d16, d17, d18}, [r0, :64]
@ vst3.16 {d16, d17, d18}, [r0]
@ vst3.32 {d16, d17, d18}, [r0]
@ vst3.8 {d16, d18, d20}, [r0, :64]!
@ vst3.8 {d17, d19, d21}, [r0, :64]!
@ vst3.16 {d16, d18, d20}, [r0]!
@ vst3.16 {d17, d19, d21}, [r0]!
@ vst3.32 {d16, d18, d20}, [r0]!
@ vst3.32 {d17, d19, d21}, [r0]!
@ FIXME: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf4]
@ FIXME: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf4]
@ FIXME: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf4]
@ FIXME: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4]
@ FIXME: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf4]
@ FIXME: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf4]
@ FIXME: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf4]
@ FIXME: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf4]
@ FIXME: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf4]
@ vst4.8 {d16, d17, d18, d19}, [r0, :64]
@ vst4.16 {d16, d17, d18, d19}, [r0, :128]
@ vst4.8 {d16, d18, d20, d22}, [r0, :256]!
@ vst4.8 {d17, d19, d21, d23}, [r0, :256]!
@ vst4.16 {d16, d18, d20, d22}, [r0]!
@ vst4.16 {d17, d19, d21, d23}, [r0]!
@ vst4.32 {d16, d18, d20, d22}, [r0]!
@ vst4.32 {d17, d19, d21, d23}, [r0]!
@ FIXME: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf4]
@ FIXME: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf4]
@ FIXME: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf4]
@ FIXME: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf4]
@ FIXME: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf4]
@ FIXME: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf4]
@ FIXME: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf4]
@ FIXME: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4]
ARM enable a few more tests. llvm-svn: 146985
2011-12-21 04:03:00 +08:00
vst2.8 {d16[1], d17[1]}, [r0, :16]
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
2012-01-24 03:39:08 +08:00
vst2.p16 {d16[1], d17[1]}, [r0, :32]
vst2.i32 {d16[1], d17[1]}, [r0]
vst2.u16 {d17[1], d19[1]}, [r0]
vst2.f32 {d17[0], d19[0]}, [r0, :64]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. llvm-svn: 142583
2011-10-20 23:04:25 +08:00
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. llvm-svn: 146605
2011-12-15 07:25:46 +08:00
vst2.8 {d2[4], d3[4]}, [r2], r3
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
2012-01-24 03:39:08 +08:00
vst2.u8 {d2[4], d3[4]}, [r2]!
vst2.p8 {d2[4], d3[4]}, [r2]
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. llvm-svn: 146605
2011-12-15 07:25:46 +08:00
ARM assembly parsing and encoding for VST2 single-element, double spaced. llvm-svn: 146990
2011-12-21 04:46:29 +08:00
vst2.16 {d17[1], d19[1]}, [r0]
vst2.32 {d17[0], d19[0]}, [r0, :64]
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
2012-01-24 03:39:08 +08:00
vst2.i16 {d7[1], d9[1]}, [r1]!
ARM assembly parsing and encoding for VST2 single-element, double spaced. llvm-svn: 146990
2011-12-21 04:46:29 +08:00
vst2.32 {d6[0], d8[0]}, [r2, :64]!
vst2.16 {d2[1], d4[1]}, [r3], r5
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
2012-01-24 03:39:08 +08:00
vst2.u32 {d5[0], d7[0]}, [r4, :64], r7
ARM assembly parsing and encoding for VST2 single-element, double spaced. llvm-svn: 146990
2011-12-21 04:46:29 +08:00
ARM enable a few more tests. llvm-svn: 146985
2011-12-21 04:03:00 +08:00
@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. llvm-svn: 146605
2011-12-15 07:25:46 +08:00
@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4]
ARM assembly parsing and encoding for VST2 single-element, double spaced. llvm-svn: 146990
2011-12-21 04:46:29 +08:00
@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. llvm-svn: 142583
2011-10-20 23:04:25 +08:00
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. llvm-svn: 146605
2011-12-15 07:25:46 +08:00
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4]
ARM assembly parsing and encoding for VST2 single-element, double spaced. llvm-svn: 146990
2011-12-21 04:46:29 +08:00
@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4]
@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4]
@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4]
@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. llvm-svn: 142583
2011-10-20 23:04:25 +08:00
@ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
@ vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
@ vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
@ vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
@ vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
@ FIXME: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf4]
@ FIXME: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf4]
@ FIXME: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4]
@ FIXME: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4]
@ FIXME: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4]
ARM parsing datatype suffix variants for non-writeback VST1 instructions. rdar://10435076 llvm-svn: 144593
2011-11-15 07:43:46 +08:00
@ Spot-check additional size-suffix aliases.
vst1.8 {d2}, [r2]
vst1.p8 {d2}, [r2]
vst1.u8 {d2}, [r2]
vst1.8 {q2}, [r2]
vst1.p8 {q2}, [r2]
vst1.u8 {q2}, [r2]
vst1.f32 {q2}, [r2]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4]