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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir

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AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_sss
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_sss
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = COPY $sgpr3
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_ssv
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_ssv
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY3]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
%2:_(s32) = COPY $sgpr2
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%3:_(s32) = COPY $vgpr0
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_svs
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_svs
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY3]], [[COPY5]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2
%3:_(s32) = COPY $vgpr0
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %3, %2
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_svv
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_svv
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY2]], [[COPY3]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_vss
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_vss
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY3]]
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY4]], [[COPY5]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(s32) = G_SELECT %4, %0, %1
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_vsv
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_vsv
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY4]], [[COPY3]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s32) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_SELECT %4, %0, %3
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_vvs
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_vvs
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s32) = COPY $vgpr2
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s32) = G_SELECT %4, %3, %0
...
---
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
name: select_s32_vvv
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
AMDGPU/GlobalISel: Legalize more types for select llvm-svn: 351599
2019-01-19 05:42:55 +08:00
; CHECK-LABEL: name: select_s32_vvv
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
AMDGPU/GlobalISel: Introduce vcc reg bank I'm not entirely sure this is the correct thing to do with the global isel philosophy, but I think this is necessary to handle how differently SGPRs are used normally vs. from a condition. For example, it makes sense to allow a copy from a VGPR to an SGPR, but it makes no sense to allow a copy from VGPRs to SGPRs used as select mask. This avoids regbankselecting strange code with a truncate feeding directly into a condition field. Now a copy is forced from sgpr(s1) to vcc, which is more sensible to handle. Some of these issues could probably avoided with making enough operations resulting in i1 illegal. I think we can't avoid this register bank for legality. For example, an i1 and where one source is from a truncate, and one source is a compare needs some kind of copy inserted to make sure both are in condition registers. llvm-svn: 350611
2019-01-08 14:30:53 +08:00
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
AMDGPU: Remove VS/SV mappings from select These would violate the constant bus restriction llvm-svn: 350517
2019-01-07 21:21:36 +08:00
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
AMDGPU/GlobalISel: Define instruction mapping for G_SELECT Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
2018-09-01 10:41:19 +08:00
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
%3:_(s32) = COPY $vgpr3
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s32) = G_SELECT %4, %2, %3
...
AMDGPU/GlobalISel: Handle split for 64-bit VALU select llvm-svn: 354065
2019-02-15 05:58:12 +08:00
---
name: select_s64_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; CHECK-LABEL: name: select_s64_sss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY $sgpr4_sgpr5
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(s64) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s64) = COPY $sgpr2_sgpr3
%3:_(s64) = COPY $sgpr4_sgpr5
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s64) = G_SELECT %4, %2, %3
...
---
name: select_s64_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-LABEL: name: select_s64_ssv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s64) = COPY $sgpr2_sgpr3
%3:_(s64) = COPY $vgpr0_vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s64) = G_SELECT %4, %2, %3
...
---
name: select_s64_svs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-LABEL: name: select_s64_svs
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s64) = COPY $sgpr2_sgpr3
%3:_(s64) = COPY $vgpr0_vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s64) = G_SELECT %4, %3, %2
...
---
name: select_s64_svv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_s64_svv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s64) = COPY $vgpr0_vgpr1
%3:_(s64) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s64) = G_SELECT %4, %2, %3
...
---
name: select_s64_vss
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr0, $vgpr1
; CHECK-LABEL: name: select_s64_vss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY3]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s64) = COPY $sgpr2_sgpr3
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(s64) = G_SELECT %4, %0, %1
...
---
name: select_s64_vsv
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_s64_vsv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s64) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s64) = G_SELECT %4, %0, %3
...
---
name: select_s64_vvs
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_s64_vvs
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s64) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(s64) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(s64) = G_SELECT %4, %3, %0
...
---
name: select_s64_vvv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: select_s64_vvv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY $vgpr4_vgpr5
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $vgpr2_vgpr3
%3:_(s64) = COPY $vgpr4_vgpr5
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(s64) = G_SELECT %4, %2, %3
...
---
name: select_v2s32_sss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; CHECK-LABEL: name: select_v2s32_sss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
; CHECK: [[COPY3:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr4_sgpr5
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[SELECT:%[0-9]+]]:sgpr(<2 x s32>) = G_SELECT [[ICMP]](s1), [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(<2 x s32>) = COPY $sgpr2_sgpr3
%3:_(<2 x s32>) = COPY $sgpr4_sgpr5
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
...
---
name: select_v2s32_ssv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-LABEL: name: select_v2s32_ssv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(<2 x s32>) = COPY $sgpr2_sgpr3
%3:_(<2 x s32>) = COPY $vgpr0_vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
...
---
name: select_v2s32_svs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-LABEL: name: select_v2s32_svs
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(<2 x s32>) = COPY $sgpr2_sgpr3
%3:_(<2 x s32>) = COPY $vgpr0_vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %3, %2
...
---
name: select_v2s32_svv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_v2s32_svv
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(<2 x s32>) = COPY $vgpr0_vgpr1
%3:_(<2 x s32>) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
...
---
name: select_v2s32_vss
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr0, $vgpr1
; CHECK-LABEL: name: select_v2s32_vss
; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY3]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(<2 x s32>) = COPY $sgpr0_sgpr1
%1:_(<2 x s32>) = COPY $sgpr2_sgpr3
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(<2 x s32>) = G_SELECT %4, %0, %1
...
---
name: select_v2s32_vsv
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_v2s32_vsv
; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(<2 x s32>) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(<2 x s32>) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(<2 x s32>) = G_SELECT %4, %0, %3
...
---
name: select_v2s32_vvs
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_v2s32_vvs
; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(<2 x s32>) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(<2 x s32>) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(<2 x s32>) = G_SELECT %4, %3, %0
...
---
name: select_v2s32_vvv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: select_v2s32_vvv
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s32>) = COPY $vgpr4_vgpr5
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(<2 x s32>) = COPY $vgpr2_vgpr3
%3:_(<2 x s32>) = COPY $vgpr4_vgpr5
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(<2 x s32>) = G_SELECT %4, %2, %3
...