forked from OSchip/llvm-project
21 lines
657 B
LLVM
21 lines
657 B
LLVM
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs | FileCheck %s
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;
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; Test that early if conversion produces LOCR with operands of the right
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; register classes.
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define void @autogen_SD4739(i8*) {
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; CHECK-NOT: Expected a GR32Bit register, but got a GRX32Bit register
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BB:
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%L34 = load i8, i8* %0
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%Cmp56 = icmp sgt i8 undef, %L34
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br label %CF246
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CF246: ; preds = %CF246, %BB
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%Sl163 = select i1 %Cmp56, i8 %L34, i8 undef
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br i1 undef, label %CF246, label %CF248
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CF248: ; preds = %CF248, %CF246
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store i8 %Sl163, i8* %0
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br label %CF248
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}
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