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llvm-project/llvm/test/CodeGen/X86/pr35918.ll

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Fix line endings. NFCI. llvm-svn: 348146
2018-12-03 22:55:09 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory. I had manually removed unused prefixes from CodeGen/X86 directory for more than 100 tests. I checked the change history for each of them at the beginning, and then I mainly focused on the format since I found all of the unused prefixes were result from either insensible copy or residuum after functional update. I think it's OK to remove the remaining X86 tests by script now. I wrote a rough script which works for me in most tests. I put it in llvm/utils temporarily for review and hope it may help other components owners. The tests in this patch are all generated by the tool and checked by update tool for the autogenerated tests. I skimmed them and checked about 30 tests and didn't find any unexpected changes. Reviewed By: mtrofin, MaskRay Differential Revision: https://reviews.llvm.org/D91496
2020-11-16 09:44:06 +08:00
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X64
Fix line endings. NFCI. llvm-svn: 348146
2018-12-03 22:55:09 +08:00
define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) nounwind {
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; X86-LABEL: fetch_r16g16_snorm_unorm8:
; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X86-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
; X86-NEXT: vpsrlw $7, %xmm0, %xmm0
; X86-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u]
; X86-NEXT: vmovd %xmm0, %ecx
; X86-NEXT: orl $-16777216, %ecx # imm = 0xFF000000
; X86-NEXT: movl %ecx, (%eax)
; X86-NEXT: retl
Fix line endings. NFCI. llvm-svn: 348146
2018-12-03 22:55:09 +08:00
;
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; X64-LABEL: fetch_r16g16_snorm_unorm8:
; X64: # %bb.0: # %entry
; X64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
; X64-NEXT: vpsrlw $7, %xmm0, %xmm0
; X64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-NEXT: vmovd %xmm0, %eax
; X64-NEXT: orl $-16777216, %eax # imm = 0xFF000000
; X64-NEXT: movl %eax, (%rdi)
; X64-NEXT: retq
Fix line endings. NFCI. llvm-svn: 348146
2018-12-03 22:55:09 +08:00
entry:
%5 = bitcast i8* %1 to <2 x i16>*
%6 = load <2 x i16>, <2 x i16>* %5, align 2
%7 = shufflevector <2 x i16> %6, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%8 = icmp sgt <4 x i16> %7, zeroinitializer
%9 = select <4 x i1> %8, <4 x i16> %7, <4 x i16> zeroinitializer
%10 = lshr <4 x i16> %9, <i16 7, i16 7, i16 7, i16 7>
%11 = shufflevector <4 x i16> %10, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
%12 = shufflevector <4 x i16> %10, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
%13 = bitcast <2 x i16> %11 to <4 x i8>
%14 = bitcast <2 x i16> %12 to <4 x i8>
%15 = shufflevector <4 x i8> %13, <4 x i8> %14, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%16 = bitcast <4 x i8> %15 to i32
%17 = and i32 %16, 65535
%18 = or i32 %17, -16777216
%19 = bitcast <4 x i8>* %0 to i32*
store i32 %18, i32* %19, align 4
ret void
}