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llvm-project/llvm/test/CodeGen/AMDGPU/llvm.rint.ll

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R600/SI: f64 frint is legal on CI llvm-svn: 206475
2014-04-18 01:06:37 +08:00
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
R600/SI: Add a stub GCNTargetMachine This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
2015-01-07 02:00:21 +08:00
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
R600/SI: Enable all tests that pass on VI without changes llvm-svn: 227214
2015-01-28 01:27:15 +08:00
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table llvm-svn: 218776
2014-10-02 01:15:17 +08:00
; FUNC-LABEL: {{^}}rint_f32:
R600/SI: f64 frint is legal on CI llvm-svn: 206475
2014-04-18 01:06:37 +08:00
; R600: RNDNE
R600/SI: Change all instruction assembly names to lowercase. This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
2014-11-05 22:50:53 +08:00
; SI: v_rndne_f32_e32
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
define void @rint_f32(float addrspace(1)* %out, float %in) {
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
entry:
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
%0 = call float @llvm.rint.f32(float %in) #0
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
store float %0, float addrspace(1)* %out
ret void
}
R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table llvm-svn: 218776
2014-10-02 01:15:17 +08:00
; FUNC-LABEL: {{^}}rint_v2f32:
R600/SI: f64 frint is legal on CI llvm-svn: 206475
2014-04-18 01:06:37 +08:00
; R600: RNDNE
; R600: RNDNE
R600/SI: Change all instruction assembly names to lowercase. This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
2014-11-05 22:50:53 +08:00
; SI: v_rndne_f32_e32
; SI: v_rndne_f32_e32
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
define void @rint_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
entry:
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
%0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in) #0
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
store <2 x float> %0, <2 x float> addrspace(1)* %out
ret void
}
R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table llvm-svn: 218776
2014-10-02 01:15:17 +08:00
; FUNC-LABEL: {{^}}rint_v4f32:
R600/SI: f64 frint is legal on CI llvm-svn: 206475
2014-04-18 01:06:37 +08:00
; R600: RNDNE
; R600: RNDNE
; R600: RNDNE
; R600: RNDNE
R600/SI: Change all instruction assembly names to lowercase. This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
2014-11-05 22:50:53 +08:00
; SI: v_rndne_f32_e32
; SI: v_rndne_f32_e32
; SI: v_rndne_f32_e32
; SI: v_rndne_f32_e32
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
define void @rint_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
entry:
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
%0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in) #0
R600: Expand vector FRINT ops Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
2013-08-17 07:51:33 +08:00
store <4 x float> %0, <4 x float> addrspace(1)* %out
ret void
}
declare float @llvm.rint.f32(float) #0
declare <2 x float> @llvm.rint.v2f32(<2 x float>) #0
declare <4 x float> @llvm.rint.v4f32(<4 x float>) #0
R600: Mostly remove remaining AMDIL intrinsics. Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
2014-06-13 05:15:44 +08:00
attributes #0 = { nounwind readnone }