2015-09-23 02:19:46 +08:00
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//===- Target.cpp ---------------------------------------------------------===//
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//
|
2019-01-19 16:50:56 +08:00
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|
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2015-09-23 02:19:46 +08:00
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//
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//===----------------------------------------------------------------------===//
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2015-10-14 03:51:57 +08:00
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//
|
2015-10-16 03:52:27 +08:00
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// Machine-specific things, such as applying relocations, creation of
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// GOT or PLT entries, etc., are handled in this file.
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//
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2016-08-25 00:36:41 +08:00
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// Refer the ELF spec for the single letter variables, S, A or P, used
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2016-04-13 09:40:19 +08:00
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// in this file.
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2015-10-14 03:51:57 +08:00
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//
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2016-04-23 09:10:15 +08:00
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// Some functions defined in this file has "relaxTls" as part of their names.
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// They do peephole optimization for TLS variables by rewriting instructions.
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// They are not part of the ABI but optional optimization, so you can skip
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// them if you are not interested in how TLS variables are optimized.
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// See the following paper for the details.
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//
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// Ulrich Drepper, ELF Handling For Thread-Local Storage
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// http://www.akkadia.org/drepper/tls.pdf
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//
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2015-10-14 03:51:57 +08:00
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//===----------------------------------------------------------------------===//
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2015-09-23 02:19:46 +08:00
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#include "Target.h"
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2016-04-01 05:26:23 +08:00
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#include "InputFiles.h"
|
2015-10-09 04:06:07 +08:00
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#include "OutputSections.h"
|
2016-12-21 08:05:39 +08:00
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#include "SymbolTable.h"
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2015-09-30 07:22:16 +08:00
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#include "Symbols.h"
|
[lld] unified COFF and ELF error handling on new Common/ErrorHandler
Summary:
The COFF linker and the ELF linker have long had similar but separate
Error.h and Error.cpp files to implement error handling. This change
introduces new error handling code in Common/ErrorHandler.h, changes the
COFF and ELF linkers to use it, and removes the old, separate
implementations.
Reviewers: ruiu
Reviewed By: ruiu
Subscribers: smeenai, jyknight, emaste, sdardis, nemanjai, nhaehnle, mgorny, javed.absar, kbarton, fedor.sergeev, llvm-commits
Differential Revision: https://reviews.llvm.org/D39259
llvm-svn: 316624
2017-10-26 06:28:38 +08:00
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#include "lld/Common/ErrorHandler.h"
|
2015-09-23 04:54:08 +08:00
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#include "llvm/Object/ELF.h"
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2015-09-23 02:19:46 +08:00
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using namespace llvm;
|
2015-09-23 04:54:08 +08:00
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using namespace llvm::object;
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2015-09-23 02:19:46 +08:00
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using namespace llvm::ELF;
|
2017-06-17 01:32:43 +08:00
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using namespace lld;
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using namespace lld::elf;
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|
2019-03-29 01:05:09 +08:00
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const TargetInfo *elf::target;
|
2015-09-23 02:19:46 +08:00
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|
2017-10-12 06:49:24 +08:00
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|
std::string lld::toString(RelType type) {
|
2017-01-26 05:27:59 +08:00
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|
StringRef s = getELFRelocationTypeName(elf::config->emachine, type);
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|
|
if (s == "Unknown")
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|
return ("Unknown (" + Twine(type) + ")").str();
|
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|
return s;
|
2017-01-06 18:04:08 +08:00
|
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|
}
|
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|
2017-06-17 04:15:03 +08:00
|
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|
TargetInfo *elf::getTarget() {
|
2017-06-17 01:32:43 +08:00
|
|
|
switch (config->emachine) {
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|
|
case EM_386:
|
|
|
|
case EM_IAMCU:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getX86TargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_AARCH64:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getAArch64TargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_AMDGPU:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getAMDGPUTargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_ARM:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getARMTargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_AVR:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getAVRTargetInfo();
|
2018-06-14 02:45:25 +08:00
|
|
|
case EM_HEXAGON:
|
|
|
|
return getHexagonTargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_MIPS:
|
|
|
|
switch (config->ekind) {
|
|
|
|
case ELF32LEKind:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getMipsTargetInfo<ELF32LE>();
|
2017-06-17 01:32:43 +08:00
|
|
|
case ELF32BEKind:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getMipsTargetInfo<ELF32BE>();
|
2017-06-17 01:32:43 +08:00
|
|
|
case ELF64LEKind:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getMipsTargetInfo<ELF64LE>();
|
2017-06-17 01:32:43 +08:00
|
|
|
case ELF64BEKind:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getMipsTargetInfo<ELF64BE>();
|
2017-06-17 01:32:43 +08:00
|
|
|
default:
|
2018-11-02 04:08:29 +08:00
|
|
|
llvm_unreachable("unsupported MIPS target");
|
2017-06-17 01:32:43 +08:00
|
|
|
}
|
2019-01-10 21:43:06 +08:00
|
|
|
case EM_MSP430:
|
|
|
|
return getMSP430TargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_PPC:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getPPCTargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_PPC64:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getPPC64TargetInfo();
|
2018-08-10 01:59:56 +08:00
|
|
|
case EM_RISCV:
|
|
|
|
return getRISCVTargetInfo();
|
2017-06-29 01:05:39 +08:00
|
|
|
case EM_SPARCV9:
|
|
|
|
return getSPARCV9TargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
case EM_X86_64:
|
2017-06-17 04:15:03 +08:00
|
|
|
return getX86_64TargetInfo();
|
2017-06-17 01:32:43 +08:00
|
|
|
}
|
2018-11-02 04:08:29 +08:00
|
|
|
llvm_unreachable("unknown target machine");
|
2017-06-17 01:32:43 +08:00
|
|
|
}
|
2015-10-15 05:30:32 +08:00
|
|
|
|
2018-03-21 17:19:34 +08:00
|
|
|
template <class ELFT> static ErrorPlace getErrPlace(const uint8_t *loc) {
|
2017-02-27 10:32:08 +08:00
|
|
|
for (InputSectionBase *d : inputSections) {
|
2018-07-02 22:13:11 +08:00
|
|
|
auto *isec = cast<InputSection>(d);
|
|
|
|
if (!isec->getParent())
|
2016-12-21 08:05:39 +08:00
|
|
|
continue;
|
|
|
|
|
2019-03-01 07:11:35 +08:00
|
|
|
uint8_t *isecLoc = Out::bufferStart + isec->getParent()->offset + isec->outSecOff;
|
2017-03-08 23:44:30 +08:00
|
|
|
if (isecLoc <= loc && loc < isecLoc + isec->getSize())
|
2018-03-21 17:19:34 +08:00
|
|
|
return {isec, isec->template getLocation<ELFT>(loc - isecLoc) + ": "};
|
2016-12-21 08:05:39 +08:00
|
|
|
}
|
2018-03-21 17:19:34 +08:00
|
|
|
return {};
|
2016-12-21 08:05:39 +08:00
|
|
|
}
|
|
|
|
|
2018-03-21 17:19:34 +08:00
|
|
|
ErrorPlace elf::getErrorPlace(const uint8_t *loc) {
|
2016-12-21 08:05:39 +08:00
|
|
|
switch (config->ekind) {
|
|
|
|
case ELF32LEKind:
|
2018-03-21 17:19:34 +08:00
|
|
|
return getErrPlace<ELF32LE>(loc);
|
2016-12-21 08:05:39 +08:00
|
|
|
case ELF32BEKind:
|
2018-03-21 17:19:34 +08:00
|
|
|
return getErrPlace<ELF32BE>(loc);
|
2016-12-21 08:05:39 +08:00
|
|
|
case ELF64LEKind:
|
2018-03-21 17:19:34 +08:00
|
|
|
return getErrPlace<ELF64LE>(loc);
|
2016-12-21 08:05:39 +08:00
|
|
|
case ELF64BEKind:
|
2018-03-21 17:19:34 +08:00
|
|
|
return getErrPlace<ELF64BE>(loc);
|
2016-12-21 08:05:39 +08:00
|
|
|
default:
|
|
|
|
llvm_unreachable("unknown ELF type");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-23 02:19:46 +08:00
|
|
|
TargetInfo::~TargetInfo() {}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
int64_t TargetInfo::getImplicitAddend(const uint8_t *buf, RelType type) const {
|
2016-03-30 20:40:38 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
bool TargetInfo::usesOnlyLowPageBits(RelType type) const { return false; }
|
2015-12-11 16:59:37 +08:00
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
bool TargetInfo::needsThunk(RelExpr expr, RelType type, const InputFile *file,
|
2017-11-04 05:21:47 +08:00
|
|
|
uint64_t branchAddr, const Symbol &s) const {
|
2017-02-01 18:26:03 +08:00
|
|
|
return false;
|
2016-04-01 05:26:23 +08:00
|
|
|
}
|
|
|
|
|
2018-10-17 01:13:01 +08:00
|
|
|
bool TargetInfo::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
|
|
|
|
uint8_t stOther) const {
|
2018-07-18 07:16:02 +08:00
|
|
|
llvm_unreachable("Target doesn't support split stacks.");
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
bool TargetInfo::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
|
2017-07-18 00:54:29 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-11-04 05:21:47 +08:00
|
|
|
void TargetInfo::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
|
2016-12-09 17:59:54 +08:00
|
|
|
writeGotPlt(buf, s);
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
RelExpr TargetInfo::adjustRelaxExpr(RelType type, const uint8_t *data,
|
2016-06-05 06:58:54 +08:00
|
|
|
RelExpr expr) const {
|
[ELF] - Implemented support for test/binop relaxations from latest ABI.
Patch implements next relaxation from latest ABI:
"Convert memory operand of test and binop into immediate operand, where binop is one of adc, add, and, cmp, or,
sbb, sub, xor instructions, when position-independent code is disabled."
It is described in System V Application Binary Interface AMD64 Architecture Processor
Supplement Draft Version 0.99.8 (https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-r249.pdf,
B.2 "B.2 Optimize GOTPCRELX Relocations").
Differential revision: http://reviews.llvm.org/D20793
llvm-svn: 271405
2016-06-02 00:45:30 +08:00
|
|
|
return expr;
|
2016-05-25 22:31:37 +08:00
|
|
|
}
|
|
|
|
|
[PPC64] toc-indirect to toc-relative relaxation
This is based on D54720 by Sean Fertile.
When accessing a global symbol which is not defined in the translation unit,
compilers will generate instructions that load the address from the toc entry.
If the symbol is defined, non-preemptable, and addressable with a 32-bit
signed offset from the toc pointer, the address can be computed
directly. e.g.
addis 3, 2, .LC0@toc@ha # R_PPC64_TOC16_HA
ld 3, .LC0@toc@l(3) # R_PPC64_TOC16_LO_DS, load the address from a .toc entry
ld/lwa 3, 0(3) # load the value from the address
.section .toc,"aw",@progbits
.LC0: .tc var[TC],var
can be relaxed to
addis 3,2,var@toc@ha # this may be relaxed to a nop,
addi 3,3,var@toc@l # then this becomes addi 3,2,var@toc
ld/lwa 3, 0(3) # load the value from the address
We can delete the test ppc64-got-indirect.s as its purpose is covered by
newly added ppc64-toc-relax.s and ppc64-toc-relax-constants.s
Reviewed By: ruiu, sfertile
Differential Revision: https://reviews.llvm.org/D60958
llvm-svn: 360112
2019-05-07 12:26:05 +08:00
|
|
|
void TargetInfo::relaxGot(uint8_t *loc, RelType type, uint64_t val) const {
|
2016-05-25 22:31:37 +08:00
|
|
|
llvm_unreachable("Should not have claimed to be relaxable");
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void TargetInfo::relaxTlsGdToLe(uint8_t *loc, RelType type,
|
2016-04-13 09:40:19 +08:00
|
|
|
uint64_t val) const {
|
2016-03-17 03:03:58 +08:00
|
|
|
llvm_unreachable("Should not have claimed to be relaxable");
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void TargetInfo::relaxTlsGdToIe(uint8_t *loc, RelType type,
|
2016-04-13 09:40:19 +08:00
|
|
|
uint64_t val) const {
|
2016-03-17 03:03:58 +08:00
|
|
|
llvm_unreachable("Should not have claimed to be relaxable");
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void TargetInfo::relaxTlsIeToLe(uint8_t *loc, RelType type,
|
2016-04-13 09:40:19 +08:00
|
|
|
uint64_t val) const {
|
2016-03-17 03:03:58 +08:00
|
|
|
llvm_unreachable("Should not have claimed to be relaxable");
|
|
|
|
}
|
|
|
|
|
2017-10-12 06:49:24 +08:00
|
|
|
void TargetInfo::relaxTlsLdToLe(uint8_t *loc, RelType type,
|
2016-04-13 09:40:19 +08:00
|
|
|
uint64_t val) const {
|
2016-03-17 03:03:58 +08:00
|
|
|
llvm_unreachable("Should not have claimed to be relaxable");
|
2015-11-26 05:46:05 +08:00
|
|
|
}
|
2017-10-10 18:09:35 +08:00
|
|
|
|
2019-03-29 01:05:09 +08:00
|
|
|
uint64_t TargetInfo::getImageBase() const {
|
2017-10-10 18:09:35 +08:00
|
|
|
// Use -image-base if set. Fall back to the target default if not.
|
|
|
|
if (config->imageBase)
|
|
|
|
return *config->imageBase;
|
|
|
|
return config->isPic ? 0 : defaultImageBase;
|
|
|
|
}
|