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llvm-project/llvm/test/CodeGen/X86/vec_shuffle-27.ll

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Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
2010-12-20 07:55:53 +08:00
; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s
Improved shuffle normalization to avoid using extract/build when we can extract using different indexes for two vectors. Added a few tests for vector shuffles. llvm-svn: 59399
2008-11-16 13:06:27 +08:00
; ModuleID = 'vec_shuffle-27.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-apple-cl.1.0"
define <8 x float> @my2filter4_1d(<4 x float> %a, <8 x float> %T0, <8 x float> %T1) nounwind readnone {
entry:
Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
2010-12-20 07:55:53 +08:00
; CHECK: subps
; CHECK: mulps
; CHECK: addps
; CHECK: subps
; CHECK: mulps
; CHECK: addps
Improved shuffle normalization to avoid using extract/build when we can extract using different indexes for two vectors. Added a few tests for vector shuffles. llvm-svn: 59399
2008-11-16 13:06:27 +08:00
%tmp7 = shufflevector <4 x float> %a, <4 x float> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3 > ; <<8 x float>> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%sub = fsub <8 x float> %T1, %T0 ; <<8 x float>> [#uses=1]
%mul = fmul <8 x float> %sub, %tmp7 ; <<8 x float>> [#uses=1]
%add = fadd <8 x float> %mul, %T0 ; <<8 x float>> [#uses=1]
Improved shuffle normalization to avoid using extract/build when we can extract using different indexes for two vectors. Added a few tests for vector shuffles. llvm-svn: 59399
2008-11-16 13:06:27 +08:00
ret <8 x float> %add
}
Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
2010-12-20 07:55:53 +08:00
Add comment for testcase for 122206 llvm-svn: 122210
2010-12-20 08:54:26 +08:00
; Test case for r122206
Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
2010-12-20 07:55:53 +08:00
define void @test2(<4 x i64>* %ap, <4 x i64>* %bp) nounwind {
entry:
Add comment for testcase for 122206 llvm-svn: 122210
2010-12-20 08:54:26 +08:00
; CHECK: movdqa
Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
2010-12-20 07:55:53 +08:00
%a = load <4 x i64> * %ap
%b = load <4 x i64> * %bp
%mulaa = mul <4 x i64> %a, %a
%mulbb = mul <4 x i64> %b, %b
%mulab = mul <4 x i64> %a, %b
%vect1271 = shufflevector <4 x i64> %mulaa, <4 x i64> %mulbb, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
%vect1272 = shufflevector <4 x i64> %mulaa, <4 x i64> %mulbb, <4 x i32> <i32 1, i32 5, i32 undef, i32 undef>
%vect1487 = shufflevector <4 x i64> %vect1271, <4 x i64> %mulab, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
%vect1488 = shufflevector <4 x i64> %vect1272, <4 x i64> %mulab, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
store <4 x i64> %vect1487, <4 x i64>* %ap
store <4 x i64> %vect1488, <4 x i64>* %bp
ret void;
}