2013-04-26 04:29:37 +08:00
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//===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2014-07-17 04:18:49 +08:00
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// This file defines the pass that finds instructions that can be
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// re-written as LEA instructions in order to reduce pipeline delays.
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2015-11-11 19:44:31 +08:00
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// When optimizing for size it replaces suitable LEAs with INC or DEC.
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2013-04-26 04:29:37 +08:00
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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2018-04-13 23:09:39 +08:00
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#include "llvm/CodeGen/TargetSchedule.h"
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2013-04-26 04:29:37 +08:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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2017-05-18 16:11:50 +08:00
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namespace llvm {
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void initializeFixupLEAPassPass(PassRegistry &);
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}
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#define FIXUPLEA_DESC "X86 LEA Fixup"
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#define FIXUPLEA_NAME "x86-fixup-LEAs"
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#define DEBUG_TYPE FIXUPLEA_NAME
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2014-04-22 10:41:26 +08:00
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2013-04-26 04:29:37 +08:00
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STATISTIC(NumLEAs, "Number of LEA instructions created");
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namespace {
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2014-06-04 05:01:35 +08:00
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class FixupLEAPass : public MachineFunctionPass {
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enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
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2017-05-18 16:11:50 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief Loop over all of the instructions in the basic block
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/// replacing applicable instructions with LEA instructions,
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/// where appropriate.
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bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
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2013-04-26 04:29:37 +08:00
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2013-04-26 05:31:33 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief Given a machine register, look for the instruction
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/// which writes it in the current basic block. If found,
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/// try to replace it with an equivalent LEA instruction.
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2015-06-19 09:53:21 +08:00
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/// If replacement succeeds, then also process the newly created
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2014-06-04 05:01:35 +08:00
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/// instruction.
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void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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2013-04-26 05:31:33 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief Given a memory access or LEA instruction
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/// whose address mode uses a base and/or index register, look for
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/// an opportunity to replace the instruction which sets the base or index
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/// register with an equivalent LEA instruction.
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void processInstruction(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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2013-04-26 05:31:33 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief Given a LEA instruction which is unprofitable
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/// on Silvermont try to replace it with an equivalent ADD instruction
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void processInstructionForSLM(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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2014-05-20 16:55:50 +08:00
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2017-05-18 16:11:50 +08:00
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/// \brief Given a LEA instruction which is unprofitable
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/// on SNB+ try to replace it with other instructions.
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/// According to Intel's Optimization Reference Manual:
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/// " For LEA instructions with three source operands and some specific
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/// situations, instruction latency has increased to 3 cycles, and must
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/// dispatch via port 1:
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/// - LEA that has all three source operands: base, index, and offset
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/// - LEA that uses base and index registers where the base is EBP, RBP,
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/// or R13
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/// - LEA that uses RIP relative addressing mode
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/// - LEA that uses 16-bit addressing mode "
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/// This function currently handles the first 2 cases only.
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MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
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MachineFunction::iterator MFI);
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2015-11-11 19:44:31 +08:00
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/// \brief Look for LEAs that add 1 to reg or subtract 1 from reg
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/// and convert them to INC or DEC respectively.
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bool fixupIncDec(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) const;
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2014-06-04 05:01:35 +08:00
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/// \brief Determine if an instruction references a machine register
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/// and, if so, whether it reads or writes the register.
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RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
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2013-04-26 05:31:33 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief Step backwards through a basic block, looking
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/// for an instruction which writes a register within
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/// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
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MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
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MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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2013-04-26 05:31:33 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief if an instruction can be converted to an
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/// equivalent LEA, insert the new instruction into the basic block
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/// and return a pointer to it. Otherwise, return zero.
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MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI) const;
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2013-04-26 04:29:37 +08:00
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2014-06-04 05:01:35 +08:00
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public:
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2017-05-18 16:11:50 +08:00
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static char ID;
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StringRef getPassName() const override { return FIXUPLEA_DESC; }
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FixupLEAPass() : MachineFunctionPass(ID) {
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initializeFixupLEAPassPass(*PassRegistry::getPassRegistry());
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}
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2013-04-26 04:29:37 +08:00
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2014-06-04 05:01:35 +08:00
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/// \brief Loop over all of the basic blocks,
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/// replacing instructions by equivalent LEA instructions
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/// if needed and when possible.
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bool runOnMachineFunction(MachineFunction &MF) override;
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2013-04-26 04:29:37 +08:00
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2016-04-05 01:09:25 +08:00
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// This pass runs after regalloc and doesn't support VReg operands.
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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2016-08-25 09:27:13 +08:00
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MachineFunctionProperties::Property::NoVRegs);
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2016-04-05 01:09:25 +08:00
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}
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2014-06-04 05:01:35 +08:00
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private:
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2018-04-13 23:09:39 +08:00
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TargetSchedModel TSM;
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2014-06-04 05:01:35 +08:00
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MachineFunction *MF;
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const X86InstrInfo *TII; // Machine instruction info.
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2015-11-11 19:44:31 +08:00
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bool OptIncDec;
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bool OptLEA;
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2014-06-04 05:01:35 +08:00
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};
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2017-05-17 03:55:03 +08:00
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}
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2017-05-17 00:01:36 +08:00
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2017-05-18 16:11:50 +08:00
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char FixupLEAPass::ID = 0;
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INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
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2013-04-26 04:29:37 +08:00
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MachineInstr *
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FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
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2013-04-26 05:31:33 +08:00
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MachineBasicBlock::iterator &MBBI) const {
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2016-06-30 08:01:54 +08:00
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MachineInstr &MI = *MBBI;
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switch (MI.getOpcode()) {
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2014-05-20 16:55:50 +08:00
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case X86::MOV32rr:
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2013-04-26 04:29:37 +08:00
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case X86::MOV64rr: {
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2016-06-30 08:01:54 +08:00
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const MachineOperand &Src = MI.getOperand(1);
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const MachineOperand &Dest = MI.getOperand(0);
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MachineInstr *NewMI =
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BuildMI(*MF, MI.getDebugLoc(),
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TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
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: X86::LEA64r))
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2017-01-13 17:58:52 +08:00
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.add(Dest)
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.add(Src)
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2016-06-30 08:01:54 +08:00
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.addImm(1)
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.addReg(0)
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.addImm(0)
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.addReg(0);
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2014-06-04 05:01:35 +08:00
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MFI->insert(MBBI, NewMI); // Insert the new inst
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2013-04-26 04:29:37 +08:00
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return NewMI;
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}
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri_DB:
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case X86::ADD32ri8_DB:
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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2016-06-30 08:01:54 +08:00
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if (!MI.getOperand(2).isImm()) {
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2013-04-26 04:29:37 +08:00
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// convertToThreeAddress will call getImm()
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// which requires isImm() to be true
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2014-04-25 13:30:21 +08:00
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return nullptr;
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2013-04-26 04:29:37 +08:00
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}
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2013-10-01 07:51:22 +08:00
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break;
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2013-10-01 07:18:42 +08:00
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case X86::ADD16rr:
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case X86::ADD16rr_DB:
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2016-06-30 08:01:54 +08:00
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if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
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2013-10-01 07:18:42 +08:00
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// if src1 != src2, then convertToThreeAddress will
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// need to create a Virtual register, which we cannot do
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// after register allocation.
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2014-04-25 13:30:21 +08:00
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return nullptr;
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2013-10-01 07:18:42 +08:00
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}
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2013-04-26 04:29:37 +08:00
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}
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2016-06-30 08:01:54 +08:00
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return TII->convertToThreeAddress(MFI, MI, nullptr);
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2013-04-26 04:29:37 +08:00
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}
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2014-06-04 05:01:35 +08:00
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FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
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2013-04-26 04:29:37 +08:00
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bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
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2017-12-16 06:22:58 +08:00
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if (skipFunction(Func.getFunction()))
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2016-04-27 05:44:24 +08:00
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return false;
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2014-06-04 05:01:39 +08:00
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MF = &Func;
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2015-02-20 16:01:52 +08:00
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const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>();
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2017-12-16 06:22:58 +08:00
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OptIncDec = !ST.slowIncDec() || Func.getFunction().optForMinSize();
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2017-05-18 16:11:50 +08:00
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OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA();
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2015-11-11 19:44:31 +08:00
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if (!OptLEA && !OptIncDec)
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2014-05-22 09:46:02 +08:00
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return false;
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2018-04-13 23:09:39 +08:00
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TSM.init(&Func.getSubtarget());
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2015-02-06 03:27:01 +08:00
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TII = ST.getInstrInfo();
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2013-04-26 04:29:37 +08:00
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DEBUG(dbgs() << "Start X86FixupLEAs\n";);
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// Process all basic blocks.
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for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
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processBasicBlock(Func, I);
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DEBUG(dbgs() << "End X86FixupLEAs\n";);
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return true;
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}
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2014-06-04 05:01:35 +08:00
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FixupLEAPass::RegUsageState
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FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
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2013-04-26 04:29:37 +08:00
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RegUsageState RegUsage = RU_NotUsed;
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2016-07-12 11:18:50 +08:00
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MachineInstr &MI = *I;
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2013-04-26 04:29:37 +08:00
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2016-07-12 11:18:50 +08:00
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for (unsigned int i = 0; i < MI.getNumOperands(); ++i) {
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MachineOperand &opnd = MI.getOperand(i);
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2014-06-04 05:01:35 +08:00
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if (opnd.isReg() && opnd.getReg() == p.getReg()) {
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2013-04-26 04:29:37 +08:00
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if (opnd.isDef())
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return RU_Write;
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RegUsage = RU_Read;
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}
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}
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return RegUsage;
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}
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/// getPreviousInstr - Given a reference to an instruction in a basic
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/// block, return a reference to the previous instruction in the block,
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/// wrapping around to the last instruction of the block if the block
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/// branches to itself.
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2014-06-04 05:01:35 +08:00
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static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
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2013-04-26 04:29:37 +08:00
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MachineFunction::iterator MFI) {
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if (I == MFI->begin()) {
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2015-10-20 05:48:29 +08:00
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if (MFI->isPredecessor(&*MFI)) {
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2013-04-26 04:29:37 +08:00
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I = --MFI->end();
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return true;
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2014-06-04 05:01:35 +08:00
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} else
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2013-04-26 04:29:37 +08:00
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return false;
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}
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--I;
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return true;
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}
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2014-06-04 05:01:35 +08:00
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MachineBasicBlock::iterator
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FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) {
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2013-04-26 04:29:37 +08:00
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int InstrDistance = 1;
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MachineBasicBlock::iterator CurInst;
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static const int INSTR_DISTANCE_THRESHOLD = 5;
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CurInst = I;
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bool Found;
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Found = getPreviousInstr(CurInst, MFI);
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2014-06-04 05:01:35 +08:00
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while (Found && I != CurInst) {
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2013-04-26 04:29:37 +08:00
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if (CurInst->isCall() || CurInst->isInlineAsm())
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break;
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if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
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break; // too far back to make a difference
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2014-06-04 05:01:35 +08:00
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if (usesRegister(p, CurInst) == RU_Write) {
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2013-04-26 04:29:37 +08:00
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return CurInst;
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}
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2018-04-13 23:09:39 +08:00
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InstrDistance += TSM.computeInstrLatency(&*CurInst);
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2013-04-26 04:29:37 +08:00
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Found = getPreviousInstr(CurInst, MFI);
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}
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2016-07-12 11:18:50 +08:00
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return MachineBasicBlock::iterator();
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2013-04-26 04:29:37 +08:00
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}
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2017-05-18 16:11:50 +08:00
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static inline bool isLEA(const int Opcode) {
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return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
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Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
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}
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static inline bool isInefficientLEAReg(unsigned int Reg) {
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return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13;
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}
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static inline bool isRegOperand(const MachineOperand &Op) {
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return Op.isReg() && Op.getReg() != X86::NoRegister;
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}
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/// hasIneffecientLEARegs - LEA that uses base and index registers
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/// where the base is EBP, RBP, or R13
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|
static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
|
|
|
|
const MachineOperand &Index) {
|
|
|
|
return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
|
|
|
|
isRegOperand(Index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool hasLEAOffset(const MachineOperand &Offset) {
|
|
|
|
return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
|
|
|
|
}
|
|
|
|
|
|
|
|
// LEA instruction that has all three operands: offset, base and index
|
|
|
|
static inline bool isThreeOperandsLEA(const MachineOperand &Base,
|
|
|
|
const MachineOperand &Index,
|
|
|
|
const MachineOperand &Offset) {
|
|
|
|
return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int getADDrrFromLEA(int LEAOpcode) {
|
|
|
|
switch (LEAOpcode) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected LEA instruction");
|
|
|
|
case X86::LEA16r:
|
|
|
|
return X86::ADD16rr;
|
|
|
|
case X86::LEA32r:
|
|
|
|
return X86::ADD32rr;
|
|
|
|
case X86::LEA64_32r:
|
|
|
|
case X86::LEA64r:
|
|
|
|
return X86::ADD64rr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
|
|
|
|
bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
|
|
|
|
switch (LEAOpcode) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected LEA instruction");
|
|
|
|
case X86::LEA16r:
|
|
|
|
return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri;
|
|
|
|
case X86::LEA32r:
|
|
|
|
case X86::LEA64_32r:
|
|
|
|
return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
|
|
|
|
case X86::LEA64r:
|
|
|
|
return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
|
|
|
|
}
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// isLEASimpleIncOrDec - Does this LEA have one these forms:
|
|
|
|
/// lea %reg, 1(%reg)
|
|
|
|
/// lea %reg, -1(%reg)
|
2016-07-12 11:18:50 +08:00
|
|
|
static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
|
|
|
|
unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
|
|
|
|
unsigned DstReg = LEA.getOperand(0).getReg();
|
2015-11-11 19:44:31 +08:00
|
|
|
unsigned AddrDispOp = 1 + X86::AddrDisp;
|
|
|
|
return SrcReg == DstReg &&
|
2016-07-12 11:18:50 +08:00
|
|
|
LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
|
|
|
|
LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
|
|
|
|
LEA.getOperand(AddrDispOp).isImm() &&
|
|
|
|
(LEA.getOperand(AddrDispOp).getImm() == 1 ||
|
|
|
|
LEA.getOperand(AddrDispOp).getImm() == -1);
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
|
|
|
|
MachineFunction::iterator MFI) const {
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineInstr &MI = *I;
|
|
|
|
int Opcode = MI.getOpcode();
|
2015-11-11 19:44:31 +08:00
|
|
|
if (!isLEA(Opcode))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
|
|
|
|
int NewOpcode;
|
2016-07-12 11:18:50 +08:00
|
|
|
bool isINC = MI.getOperand(4).getImm() == 1;
|
2015-11-11 19:44:31 +08:00
|
|
|
switch (Opcode) {
|
|
|
|
case X86::LEA16r:
|
|
|
|
NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
|
|
|
|
break;
|
|
|
|
case X86::LEA32r:
|
|
|
|
case X86::LEA64_32r:
|
|
|
|
NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
|
|
|
|
break;
|
|
|
|
case X86::LEA64r:
|
|
|
|
NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *NewMI =
|
2016-07-12 11:18:50 +08:00
|
|
|
BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
|
2017-01-13 17:58:52 +08:00
|
|
|
.add(MI.getOperand(0))
|
|
|
|
.add(MI.getOperand(1));
|
2015-11-11 19:44:31 +08:00
|
|
|
MFI->erase(I);
|
|
|
|
I = static_cast<MachineBasicBlock::iterator>(NewMI);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-04 05:01:35 +08:00
|
|
|
void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
|
2013-04-26 04:29:37 +08:00
|
|
|
MachineFunction::iterator MFI) {
|
|
|
|
// Process a load, store, or LEA instruction.
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineInstr &MI = *I;
|
|
|
|
const MCInstrDesc &Desc = MI.getDesc();
|
2016-04-28 13:58:46 +08:00
|
|
|
int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (AddrOffset >= 0) {
|
|
|
|
AddrOffset += X86II::getOperandBias(Desc);
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (p.isReg() && p.getReg() != X86::ESP) {
|
|
|
|
seekLEAFixup(p, I, MFI);
|
|
|
|
}
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (q.isReg() && q.getReg() != X86::ESP) {
|
|
|
|
seekLEAFixup(q, I, MFI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-04 05:01:35 +08:00
|
|
|
void FixupLEAPass::seekLEAFixup(MachineOperand &p,
|
|
|
|
MachineBasicBlock::iterator &I,
|
2013-04-26 04:29:37 +08:00
|
|
|
MachineFunction::iterator MFI) {
|
|
|
|
MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
|
2016-07-12 11:18:50 +08:00
|
|
|
if (MBI != MachineBasicBlock::iterator()) {
|
2014-06-04 05:01:35 +08:00
|
|
|
MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (NewMI) {
|
|
|
|
++NumLEAs;
|
2014-05-20 16:55:50 +08:00
|
|
|
DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
|
2013-04-26 04:29:37 +08:00
|
|
|
// now to replace with an equivalent LEA...
|
2014-05-20 16:55:50 +08:00
|
|
|
DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
|
2013-04-26 04:29:37 +08:00
|
|
|
MFI->erase(MBI);
|
|
|
|
MachineBasicBlock::iterator J =
|
2014-06-04 05:01:35 +08:00
|
|
|
static_cast<MachineBasicBlock::iterator>(NewMI);
|
2013-04-26 04:29:37 +08:00
|
|
|
processInstruction(J, MFI);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-20 16:55:50 +08:00
|
|
|
void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
|
|
|
|
MachineFunction::iterator MFI) {
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineInstr &MI = *I;
|
2017-05-18 16:11:50 +08:00
|
|
|
const int Opcode = MI.getOpcode();
|
|
|
|
if (!isLEA(Opcode))
|
2014-05-20 16:55:50 +08:00
|
|
|
return;
|
2016-07-12 11:18:50 +08:00
|
|
|
if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
|
2014-05-20 16:55:50 +08:00
|
|
|
!TII->isSafeToClobberEFLAGS(*MFI, I))
|
|
|
|
return;
|
2016-07-12 11:18:50 +08:00
|
|
|
const unsigned DstR = MI.getOperand(0).getReg();
|
|
|
|
const unsigned SrcR1 = MI.getOperand(1).getReg();
|
|
|
|
const unsigned SrcR2 = MI.getOperand(3).getReg();
|
2014-05-20 16:55:50 +08:00
|
|
|
if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
|
|
|
|
return;
|
2016-07-12 11:18:50 +08:00
|
|
|
if (MI.getOperand(2).getImm() > 1)
|
2014-05-20 16:55:50 +08:00
|
|
|
return;
|
|
|
|
DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
|
|
|
|
DEBUG(dbgs() << "FixLEA: Replaced by: ";);
|
2014-06-09 06:29:17 +08:00
|
|
|
MachineInstr *NewMI = nullptr;
|
2014-05-20 16:55:50 +08:00
|
|
|
// Make ADD instruction for two registers writing to LEA's destination
|
|
|
|
if (SrcR1 != 0 && SrcR2 != 0) {
|
2017-05-18 16:11:50 +08:00
|
|
|
const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
|
|
|
|
const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
|
|
|
|
NewMI =
|
|
|
|
BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
|
2014-05-20 16:55:50 +08:00
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
}
|
|
|
|
// Make ADD instruction for immediate
|
2016-07-12 11:18:50 +08:00
|
|
|
if (MI.getOperand(4).getImm() != 0) {
|
2017-05-18 16:11:50 +08:00
|
|
|
const MCInstrDesc &ADDri =
|
|
|
|
TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
|
2016-07-12 11:18:50 +08:00
|
|
|
const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
|
2017-05-18 16:11:50 +08:00
|
|
|
NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
|
2017-01-13 17:58:52 +08:00
|
|
|
.add(SrcR)
|
2016-07-12 11:18:50 +08:00
|
|
|
.addImm(MI.getOperand(4).getImm());
|
2014-05-20 16:55:50 +08:00
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
}
|
|
|
|
if (NewMI) {
|
|
|
|
MFI->erase(I);
|
2017-05-18 16:11:50 +08:00
|
|
|
I = NewMI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *
|
|
|
|
FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
|
|
|
|
MachineFunction::iterator MFI) {
|
|
|
|
|
|
|
|
const int LEAOpcode = MI.getOpcode();
|
|
|
|
if (!isLEA(LEAOpcode))
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
const MachineOperand &Dst = MI.getOperand(0);
|
|
|
|
const MachineOperand &Base = MI.getOperand(1);
|
|
|
|
const MachineOperand &Scale = MI.getOperand(2);
|
|
|
|
const MachineOperand &Index = MI.getOperand(3);
|
|
|
|
const MachineOperand &Offset = MI.getOperand(4);
|
|
|
|
const MachineOperand &Segment = MI.getOperand(5);
|
|
|
|
|
|
|
|
if (!(isThreeOperandsLEA(Base, Index, Offset) ||
|
|
|
|
hasInefficientLEABaseReg(Base, Index)) ||
|
|
|
|
!TII->isSafeToClobberEFLAGS(*MFI, MI) ||
|
|
|
|
Segment.getReg() != X86::NoRegister)
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
unsigned int DstR = Dst.getReg();
|
|
|
|
unsigned int BaseR = Base.getReg();
|
|
|
|
unsigned int IndexR = Index.getReg();
|
|
|
|
unsigned SSDstR =
|
|
|
|
(LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
|
|
|
|
bool IsScale1 = Scale.getImm() == 1;
|
|
|
|
bool IsInefficientBase = isInefficientLEAReg(BaseR);
|
|
|
|
bool IsInefficientIndex = isInefficientLEAReg(IndexR);
|
|
|
|
|
|
|
|
// Skip these cases since it takes more than 2 instructions
|
|
|
|
// to replace the LEA instruction.
|
|
|
|
if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
|
|
|
|
return nullptr;
|
|
|
|
if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
|
|
|
|
(IsInefficientIndex || !IsScale1))
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
const DebugLoc DL = MI.getDebugLoc();
|
|
|
|
const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
|
|
|
|
const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
|
|
|
|
DEBUG(dbgs() << "FixLEA: Replaced by: ";);
|
|
|
|
|
|
|
|
// First try to replace LEA with one or two (for the 3-op LEA case)
|
|
|
|
// add instructions:
|
|
|
|
// 1.lea (%base,%index,1), %base => add %index,%base
|
|
|
|
// 2.lea (%base,%index,1), %index => add %base,%index
|
|
|
|
if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
|
|
|
|
const MachineOperand &Src = DstR == BaseR ? Index : Base;
|
|
|
|
MachineInstr *NewMI =
|
|
|
|
BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
// Create ADD instruction for the Offset in case of 3-Ops LEA.
|
|
|
|
if (hasLEAOffset(Offset)) {
|
|
|
|
NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
}
|
|
|
|
return NewMI;
|
|
|
|
}
|
|
|
|
// If the base is inefficient try switching the index and base operands,
|
|
|
|
// otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
|
|
|
|
// lea offset(%base,%index,scale),%dst =>
|
|
|
|
// lea (%base,%index,scale); add offset,%dst
|
|
|
|
if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
|
|
|
|
MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
|
|
|
|
.add(Dst)
|
|
|
|
.add(IsInefficientBase ? Index : Base)
|
|
|
|
.add(Scale)
|
|
|
|
.add(IsInefficientBase ? Base : Index)
|
|
|
|
.addImm(0)
|
|
|
|
.add(Segment);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
// Create ADD instruction for the Offset in case of 3-Ops LEA.
|
|
|
|
if (hasLEAOffset(Offset)) {
|
|
|
|
NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
}
|
|
|
|
return NewMI;
|
|
|
|
}
|
|
|
|
// Handle the rest of the cases with inefficient base register:
|
|
|
|
assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
|
|
|
|
assert(IsInefficientBase && "efficient base should be handled already!");
|
|
|
|
|
|
|
|
// lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
|
|
|
|
if (IsScale1 && !hasLEAOffset(Offset)) {
|
2018-01-26 12:49:26 +08:00
|
|
|
bool BIK = Base.isKill() && BaseR != IndexR;
|
|
|
|
TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, BIK);
|
2017-05-18 16:11:50 +08:00
|
|
|
DEBUG(MI.getPrevNode()->dump(););
|
|
|
|
|
|
|
|
MachineInstr *NewMI =
|
|
|
|
BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
return NewMI;
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|
2017-05-18 16:11:50 +08:00
|
|
|
// lea offset(%base,%index,scale), %dst =>
|
|
|
|
// lea offset( ,%index,scale), %dst; add %base,%dst
|
|
|
|
MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode))
|
|
|
|
.add(Dst)
|
|
|
|
.addReg(0)
|
|
|
|
.add(Scale)
|
|
|
|
.add(Index)
|
|
|
|
.add(Offset)
|
|
|
|
.add(Segment);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
|
|
|
|
NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
|
|
|
|
DEBUG(NewMI->dump(););
|
|
|
|
return NewMI;
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|
|
|
|
|
2013-04-26 04:29:37 +08:00
|
|
|
bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
|
|
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|
MachineFunction::iterator MFI) {
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|
|
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|
2014-05-20 16:55:50 +08:00
|
|
|
for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
|
2015-11-11 19:44:31 +08:00
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|
|
if (OptIncDec)
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|
if (fixupIncDec(I, MFI))
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|
|
continue;
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|
|
|
if (OptLEA) {
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|
if (MF.getSubtarget<X86Subtarget>().isSLM())
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|
|
|
processInstructionForSLM(I, MFI);
|
2017-05-18 16:11:50 +08:00
|
|
|
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|
|
|
else {
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|
|
|
if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) {
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|
|
|
if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) {
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|
|
|
MFI->erase(I);
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|
|
|
I = NewMI;
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|
|
|
}
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|
|
} else
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|
|
|
processInstruction(I, MFI);
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|
|
|
}
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|
2013-04-26 04:29:37 +08:00
|
|
|
return false;
|
|
|
|
}
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