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llvm-project/llvm/test/MC/Mips/dsp/invalid.s

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[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
2015-11-13 21:14:25 +08:00
# RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dsp 2>%t1
# RUN: FileCheck %s < %t1
[mips] Range check uimm16 and fix several bugs this revealed. Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
2016-02-01 23:13:31 +08:00
extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
2015-11-13 21:14:25 +08:00
shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
[mips] Range check uimm16 and fix several bugs this revealed. Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
2016-02-01 23:13:31 +08:00
shll_s.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shll_s.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
2015-11-13 21:14:25 +08:00
shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate
[mips] Range check uimm16 and fix several bugs this revealed. Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
2016-02-01 23:13:31 +08:00
shra_r.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shra_r.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions Differential Revision: http://reviews.llvm.org/D14010 llvm-svn: 253041
2015-11-13 21:14:25 +08:00
shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
[mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
2015-12-18 16:59:37 +08:00
shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
[mips] Range check uimm16 and fix several bugs this revealed. Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
2016-02-01 23:13:31 +08:00
repl.qb $2, -1 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate
repl.qb $2, 256 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate
[mips][dsp] Modify repl.ph to accept signed immediate values Changed immediate type for repl.ph from uimm10 to simm10 as per the specs. Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33594 llvm-svn: 304918
2017-06-07 22:48:46 +08:00
repl.ph $2, -513 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
repl.ph $2, 512 # CHECK: :[[@LINE]]:15: error: expected 10-bit signed immediate
[mips] Range check uimm16 and fix several bugs this revealed. Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
2016-02-01 23:13:31 +08:00
rddsp $2, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
rddsp $2, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
[mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP instructions Differential Revision: http://reviews.llvm.org/D14429 llvm-svn: 255991
2015-12-18 16:59:37 +08:00
wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
[mips] Range check uimm16 and fix several bugs this revealed. Summary: The bugs were: * teq and similar take 4-bit unsigned immediates on microMIPS. * teqi and similar have side-effects like teq do. * shll_s.w and shra_r.w take 5-bit unsigned immediates. * The various DSP ext* instructions take a 5-bit immediate. * repl.qh takes an 8-bit unsigned immediate. * repl.ph takes a 10-bit unsigned immediate. * rddsp/wrdsp take a 10-bit unsigned immediate. * teqi and similar take signed 16-bit immediates (10-bit for microMIPS). * Out-of-range immediate macros for or/xor take a simm32/simm64 depending on architecture. I'll fix the simm64 case properly when I reach simm32. lui is a bit more lenient than GAS and accepts signed immediates in addition to unsigned. This is because MipsMCExpr can produce signed values when constant folding and it currently lacks a way of knowing it should fold to an unsigned value. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15446 llvm-svn: 259360
2016-02-01 23:13:31 +08:00
wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate