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llvm-project/llvm/test/CodeGen/AArch64/reverse-csr-restore-seq.mir

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[AArch64] Emit CSR loads in the same order as stores Optionally allow the order of restoring the callee-saved registers in the epilogue to be reversed. The flag -reverse-csr-restore-seq generates the following code: ``` stp x26, x25, [sp, #-64]! stp x24, x23, [sp, #16] stp x22, x21, [sp, #32] stp x20, x19, [sp, #48] ; [..] ldp x24, x23, [sp, #16] ldp x22, x21, [sp, #32] ldp x20, x19, [sp, #48] ldp x26, x25, [sp], #64 ret ``` Note how the CSRs are restored in the same order as they are saved. One exception to this rule is the last `ldp`, which allows us to merge the stack adjustment and the ldp into a post-index ldp. This is done by first generating: ldp x26, x27, [sp] add sp, sp, #64 which gets merged by the arm64 load store optimizer into ldp x26, x25, [sp], #64 The flag is disabled by default. llvm-svn: 327569
2018-03-15 04:34:03 +08:00
# RUN: llc -run-pass=prologepilog -reverse-csr-restore-seq -o - -mtriple=aarch64-- %s | FileCheck %s --check-prefixes=CHECK,BEFORELDSTOPT
# RUN: llc -start-before=prologepilog -stop-after=aarch64-ldst-opt -reverse-csr-restore-seq -o - -mtriple=aarch64-- %s | FileCheck %s --check-prefixes=CHECK,AFTERLDSTOPT
#
--- |
define void @foo() nounwind { entry: unreachable }
define void @bar() nounwind { entry: unreachable }
[AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true Put the first ldp at the end, so that the load-store optimizer can run and merge the ldp and the add into a post-index ldp. This didn't work in case no frame was needed and resulted in code size regressions. llvm-svn: 331044
2018-04-27 23:30:54 +08:00
define void @baz() nounwind { entry: unreachable }
[AArch64] Emit CSR loads in the same order as stores Optionally allow the order of restoring the callee-saved registers in the epilogue to be reversed. The flag -reverse-csr-restore-seq generates the following code: ``` stp x26, x25, [sp, #-64]! stp x24, x23, [sp, #16] stp x22, x21, [sp, #32] stp x20, x19, [sp, #48] ; [..] ldp x24, x23, [sp, #16] ldp x22, x21, [sp, #32] ldp x20, x19, [sp, #48] ldp x26, x25, [sp], #64 ret ``` Note how the CSRs are restored in the same order as they are saved. One exception to this rule is the last `ldp`, which allows us to merge the stack adjustment and the ldp into a post-index ldp. This is done by first generating: ldp x26, x27, [sp] add sp, sp, #64 which gets merged by the arm64 load store optimizer into ldp x26, x25, [sp], #64 The flag is disabled by default. llvm-svn: 327569
2018-03-15 04:34:03 +08:00
...
---
name: foo
# CHECK-LABEL: name: foo
tracksRegLiveness: true
body: |
bb.0:
$x19 = IMPLICIT_DEF
$x20 = IMPLICIT_DEF
$x21 = IMPLICIT_DEF
$x22 = IMPLICIT_DEF
$x23 = IMPLICIT_DEF
$x24 = IMPLICIT_DEF
$x25 = IMPLICIT_DEF
$x26 = IMPLICIT_DEF
; The local stack size is 0, so the last ldp in the sequence will also
; restore the stack.
; CHECK: $x24, $x23 = frame-destroy LDPXi $sp, 2
; CHECK-NEXT: $x22, $x21 = frame-destroy LDPXi $sp, 4
; CHECK-NEXT: $x20, $x19 = frame-destroy LDPXi $sp, 6
; Before running the load-store optimizer, we emit a ldp and an add.
; BEFORELDSTOPT-NEXT: $x26, $x25 = frame-destroy LDPXi $sp, 0
; BEFORELDSTOPT-NEXT: $sp = frame-destroy ADDXri $sp, 64, 0
; We want to make sure that after running the load-store optimizer, the ldp
; and the add get merged into a post-index ldp.
; AFTERLDSTOPT-NEXT: early-clobber $sp, $x26, $x25 = frame-destroy LDPXpost $sp, 8
RET_ReallyLR
...
---
name: bar
# CHECK-LABEL: name: bar
tracksRegLiveness: true
stack:
- { id : 0, size: 8, alignment: 4,
Describe stack-id as an enum This patch changes MIR stack-id from an integer to an enum, and adds printing/parsing support for this in MIR files. The default stack-id '0' is now renamed to 'default'. This should make MIR tests that have stack objects with different stack-ids more descriptive. It also clarifies code operating on StackID. Reviewers: arsenm, thegameg, qcolombet Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D60137 llvm-svn: 363533
2019-06-17 17:13:29 +08:00
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
[MIR] Add support for debug metadata for fixed stack objects Debug var, expr and loc were only supported for non-fixed stack objects. This patch adds the following fields to the "fixedStack:" entries, and renames the ones from "stack:" to: * debug-info-variable * debug-info-expression * debug-info-location Differential Revision: https://reviews.llvm.org/D46032 llvm-svn: 330859
2018-04-26 02:58:06 +08:00
local-offset: -4, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
[AArch64] Emit CSR loads in the same order as stores Optionally allow the order of restoring the callee-saved registers in the epilogue to be reversed. The flag -reverse-csr-restore-seq generates the following code: ``` stp x26, x25, [sp, #-64]! stp x24, x23, [sp, #16] stp x22, x21, [sp, #32] stp x20, x19, [sp, #48] ; [..] ldp x24, x23, [sp, #16] ldp x22, x21, [sp, #32] ldp x20, x19, [sp, #48] ldp x26, x25, [sp], #64 ret ``` Note how the CSRs are restored in the same order as they are saved. One exception to this rule is the last `ldp`, which allows us to merge the stack adjustment and the ldp into a post-index ldp. This is done by first generating: ldp x26, x27, [sp] add sp, sp, #64 which gets merged by the arm64 load store optimizer into ldp x26, x25, [sp], #64 The flag is disabled by default. llvm-svn: 327569
2018-03-15 04:34:03 +08:00
body: |
bb.0:
$x19 = IMPLICIT_DEF
$x20 = IMPLICIT_DEF
$x21 = IMPLICIT_DEF
$x22 = IMPLICIT_DEF
$x23 = IMPLICIT_DEF
$x24 = IMPLICIT_DEF
$x25 = IMPLICIT_DEF
$x26 = IMPLICIT_DEF
; The local stack size is not 0, and we can combine the CSR stack size with
; the local stack size. This results in rewriting the offsets for all the
; save/restores and forbids us to merge the stack adjustment and the last pop.
; In this case, there is no point of moving the first CSR pair at the end.
; CHECK: $x26, $x25 = frame-destroy LDPXi $sp, 2
; CHECK-NEXT: $x24, $x23 = frame-destroy LDPXi $sp, 4
; CHECK-NEXT: $x22, $x21 = frame-destroy LDPXi $sp, 6
; CHECK-NEXT: $x20, $x19 = frame-destroy LDPXi $sp, 8
; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 80, 0
RET_ReallyLR
...
[AArch64] Place the first ldp at the end when ReverseCSRRestoreSeq is true Put the first ldp at the end, so that the load-store optimizer can run and merge the ldp and the add into a post-index ldp. This didn't work in case no frame was needed and resulted in code size regressions. llvm-svn: 331044
2018-04-27 23:30:54 +08:00
---
# Check that the load from the offset 0 is moved at the end even when hasFP is
# false.
name: baz
# CHECK-LABEL: name: baz
alignment: 2
tracksRegLiveness: true
frameInfo:
adjustsStack: true
hasCalls: true
body: |
bb.0:
successors: %bb.1
$x0 = IMPLICIT_DEF
$x20 = IMPLICIT_DEF
$x21 = IMPLICIT_DEF
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp, implicit-def $x0
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.1
bb.1:
; CHECK: $x20, $lr = frame-destroy LDPXi $sp, 2
; BEFORELDSTOPT-NEXT: $x21 = frame-destroy LDRXui $sp, 0
; BEFORELDSTOPT-NEXT: $sp = frame-destroy ADDXri $sp, 32, 0
; AFTERLDSTOPT-NEXT: early-clobber $sp, $x21 = frame-destroy LDRXpost $sp, 32
RET_ReallyLR
...