forked from OSchip/llvm-project
49 lines
1.4 KiB
Plaintext
49 lines
1.4 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
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---
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name: redundant_zext_8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: redundant_zext_8
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
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; CHECK: $w0 = COPY [[COPY1]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr(p0) = COPY $x0
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%2:gpr(s8) = G_LOAD %1(p0) :: (load 1)
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%3:gpr(s32) = G_ZEXT %2(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: redundant_zext_16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: redundant_zext_16
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK: $w0 = COPY [[COPY1]]
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; CHECK: RET_ReallyLR implicit $w0
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%1:gpr(p0) = COPY $x0
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%2:gpr(s16) = G_LOAD %1(p0) :: (load 2)
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%3:gpr(s32) = G_ZEXT %2(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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