forked from OSchip/llvm-project
35 lines
1.6 KiB
Plaintext
35 lines
1.6 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: build_vec_f16
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; Check that s16 operands are assigned fpr as we don't have 16 bit gpr regs.
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; CHECK-LABEL: name: build_vec_f16
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
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; CHECK: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY2:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY3:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY4:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY5:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY6:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY7:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[COPY8:%[0-9]+]]:fpr(s16) = COPY [[TRUNC]](s16)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:fpr(<8 x s16>) = G_BUILD_VECTOR [[COPY1]](s16), [[COPY2]](s16), [[COPY3]](s16), [[COPY4]](s16), [[COPY5]](s16), [[COPY6]](s16), [[COPY7]](s16), [[COPY8]](s16)
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; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(s32) = COPY $w0
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%1:_(s16) = G_TRUNC %0(s32)
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%2:_(<8 x s16>) = G_BUILD_VECTOR %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16), %1(s16)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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