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llvm-project/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr...

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[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[mips] Merge MipsLongBranch and MipsHazardSchedule passes MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332977
2018-05-22 21:24:38 +08:00
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MM
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
# Test the long branch expansion of various branches
--- |
define i32 @a(double %a, double %b) {
entry:
%cmp = fcmp une double %a, %b
br i1 %cmp, label %if.then, label %return
if.then:
call void asm sideeffect ".space 810680", "~{$1}"()
ret i32 0
return:
ret i32 1
}
define i32 @b(double %a, double %b) {
entry:
%cmp = fcmp ueq double %a, %b
br i1 %cmp, label %if.then, label %return
if.then:
call void asm sideeffect ".space 810680", "~{$1}"()
ret i32 0
return:
ret i32 1
}
...
---
name: a
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 4
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$d12_64', virtual-reg: '' }
- { reg: '$d14_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MM-LABEL: name: a
; MM: bb.0.entry:
; MM: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MM: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
; MM: BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at
; MM: bb.1.entry:
; MM: successors: %bb.3(0x80000000)
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
[MIR] Add comments to INLINEASM immediate flag MachineOperands Summary: The INLINEASM MIR instructions use immediate operands to encode the values of some operands. The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature. Reviewers: SjoerdMeijer, arsenm, efriedma Reviewed By: arsenm Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78088
2020-04-14 15:24:40 +08:00
; MM: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
; MM: $v0 = LI16_MM 0
; MM: JRC16_MM undef $ra, implicit $v0
; MM: bb.3.return:
; MM: $v0 = LI16_MM 1
; MM: JRC16_MM undef $ra, implicit $v0
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
; PIC: BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
[mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions with additional flag, so instead of always lowering to lui %hi(...), addiu %lo(...) or addiu %hi(...), now they can lower to either %lo, %hi, %higher or %highest depending on the added flag. Differential Revision: https://reviews.llvm.org/D47941 llvm-svn: 334490
2018-06-12 18:23:49 +08:00
; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then:
[MIR] Add comments to INLINEASM immediate flag MachineOperands Summary: The INLINEASM MIR instructions use immediate operands to encode the values of some operands. The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature. Reviewers: SjoerdMeijer, arsenm, efriedma Reviewed By: arsenm Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78088
2020-04-14 15:24:40 +08:00
; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
; PIC: $v0 = LI16_MM 0
; PIC: JRC16_MM undef $ra, implicit $v0
; PIC: bb.4.return:
; PIC: $v0 = LI16_MM 1
; PIC: JRC16_MM undef $ra, implicit $v0
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
$f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
$v0 = LI16_MM 0
PseudoReturn undef $ra, implicit $v0
bb.2.return:
$v0 = LI16_MM 1
PseudoReturn undef $ra, implicit $v0
...
---
name: b
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 4
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$d12_64', virtual-reg: '' }
- { reg: '$d14_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MM-LABEL: name: b
; MM: bb.0.entry:
; MM: successors: %bb.2(0x30000000), %bb.1(0x50000000)
; MM: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
; MM: BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at
; MM: bb.1.entry:
; MM: successors: %bb.3(0x80000000)
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
[MIR] Add comments to INLINEASM immediate flag MachineOperands Summary: The INLINEASM MIR instructions use immediate operands to encode the values of some operands. The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature. Reviewers: SjoerdMeijer, arsenm, efriedma Reviewed By: arsenm Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78088
2020-04-14 15:24:40 +08:00
; MM: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
; MM: $v0 = LI16_MM 0
; MM: JRC16_MM undef $ra, implicit $v0
; MM: bb.3.return:
; MM: $v0 = LI16_MM 1
; MM: JRC16_MM undef $ra, implicit $v0
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; PIC: $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
; PIC: BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
[mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions with additional flag, so instead of always lowering to lui %hi(...), addiu %lo(...) or addiu %hi(...), now they can lower to either %lo, %hi, %higher or %highest depending on the added flag. Differential Revision: https://reviews.llvm.org/D47941 llvm-svn: 334490
2018-06-12 18:23:49 +08:00
; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then:
[MIR] Add comments to INLINEASM immediate flag MachineOperands Summary: The INLINEASM MIR instructions use immediate operands to encode the values of some operands. The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature. Reviewers: SjoerdMeijer, arsenm, efriedma Reviewed By: arsenm Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78088
2020-04-14 15:24:40 +08:00
; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
2018-05-16 18:03:05 +08:00
; PIC: $v0 = LI16_MM 0
; PIC: JRC16_MM undef $ra, implicit $v0
; PIC: bb.4.return:
; PIC: $v0 = LI16_MM 1
; PIC: JRC16_MM undef $ra, implicit $v0
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2(0x50000000)
liveins: $d12_64, $d14_64
$f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
bb.1.if.then:
INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
$v0 = LI16_MM 0
PseudoReturn undef $ra, implicit $v0
bb.2.return:
$v0 = LI16_MM 1
PseudoReturn undef $ra, implicit $v0
...