forked from OSchip/llvm-project
159 lines
4.8 KiB
LLVM
159 lines
4.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
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; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
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; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
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; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
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define i64 @test_max(i64* nocapture %ptr, i64 signext %val) {
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; MIPS-LABEL: test_max:
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; MIPS: # %bb.0: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: .LBB0_1: # %entry
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; MIPS-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPS-NEXT: lld $2, 0($4)
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; MIPS-NEXT: slt $3, $2, $5
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; MIPS-NEXT: move $1, $2
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; MIPS-NEXT: movn $1, $5, $3
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; MIPS-NEXT: scd $1, 0($4)
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; MIPS-NEXT: beqz $1, .LBB0_1
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; MIPS-NEXT: nop
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; MIPS-NEXT: # %bb.2: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: jr $ra
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; MIPS-NEXT: nop
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;
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; MIPSR6-LABEL: test_max:
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; MIPSR6: # %bb.0: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: .LBB0_1: # %entry
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; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPSR6-NEXT: lld $2, 0($4)
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; MIPSR6-NEXT: slt $3, $2, $5
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; MIPSR6-NEXT: seleqz $1, $2, $3
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; MIPSR6-NEXT: selnez $3, $5, $3
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; MIPSR6-NEXT: or $1, $1, $3
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; MIPSR6-NEXT: scd $1, 0($4)
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; MIPSR6-NEXT: beqzc $1, .LBB0_1
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; MIPSR6-NEXT: # %bb.2: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: jrc $ra
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entry:
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%0 = atomicrmw max i64* %ptr, i64 %val seq_cst
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ret i64 %0
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}
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define i64 @test_min(i64* nocapture %ptr, i64 signext %val) {
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; MIPS-LABEL: test_min:
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; MIPS: # %bb.0: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: .LBB1_1: # %entry
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; MIPS-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPS-NEXT: lld $2, 0($4)
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; MIPS-NEXT: slt $3, $2, $5
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; MIPS-NEXT: move $1, $2
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; MIPS-NEXT: movz $1, $5, $3
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; MIPS-NEXT: scd $1, 0($4)
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; MIPS-NEXT: beqz $1, .LBB1_1
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; MIPS-NEXT: nop
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; MIPS-NEXT: # %bb.2: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: jr $ra
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; MIPS-NEXT: nop
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;
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; MIPSR6-LABEL: test_min:
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; MIPSR6: # %bb.0: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: .LBB1_1: # %entry
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; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPSR6-NEXT: lld $2, 0($4)
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; MIPSR6-NEXT: slt $3, $2, $5
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; MIPSR6-NEXT: selnez $1, $2, $3
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; MIPSR6-NEXT: seleqz $3, $5, $3
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; MIPSR6-NEXT: or $1, $1, $3
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; MIPSR6-NEXT: scd $1, 0($4)
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; MIPSR6-NEXT: beqzc $1, .LBB1_1
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; MIPSR6-NEXT: # %bb.2: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: jrc $ra
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entry:
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%0 = atomicrmw min i64* %ptr, i64 %val seq_cst
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ret i64 %0
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}
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define i64 @test_umax(i64* nocapture %ptr, i64 zeroext %val) {
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; MIPS-LABEL: test_umax:
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; MIPS: # %bb.0: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: .LBB2_1: # %entry
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; MIPS-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPS-NEXT: lld $2, 0($4)
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; MIPS-NEXT: sltu $3, $2, $5
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; MIPS-NEXT: move $1, $2
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; MIPS-NEXT: movn $1, $5, $3
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; MIPS-NEXT: scd $1, 0($4)
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; MIPS-NEXT: beqz $1, .LBB2_1
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; MIPS-NEXT: nop
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; MIPS-NEXT: # %bb.2: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: jr $ra
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; MIPS-NEXT: nop
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;
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; MIPSR6-LABEL: test_umax:
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; MIPSR6: # %bb.0: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: .LBB2_1: # %entry
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; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPSR6-NEXT: lld $2, 0($4)
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; MIPSR6-NEXT: sltu $3, $2, $5
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; MIPSR6-NEXT: seleqz $1, $2, $3
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; MIPSR6-NEXT: selnez $3, $5, $3
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; MIPSR6-NEXT: or $1, $1, $3
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; MIPSR6-NEXT: scd $1, 0($4)
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; MIPSR6-NEXT: beqzc $1, .LBB2_1
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; MIPSR6-NEXT: # %bb.2: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: jrc $ra
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entry:
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%0 = atomicrmw umax i64* %ptr, i64 %val seq_cst
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ret i64 %0
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}
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define i64 @test_umin(i64* nocapture %ptr, i64 zeroext %val) {
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; MIPS-LABEL: test_umin:
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; MIPS: # %bb.0: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: .LBB3_1: # %entry
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; MIPS-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPS-NEXT: lld $2, 0($4)
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; MIPS-NEXT: sltu $3, $2, $5
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; MIPS-NEXT: move $1, $2
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; MIPS-NEXT: movz $1, $5, $3
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; MIPS-NEXT: scd $1, 0($4)
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; MIPS-NEXT: beqz $1, .LBB3_1
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; MIPS-NEXT: nop
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; MIPS-NEXT: # %bb.2: # %entry
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; MIPS-NEXT: sync
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; MIPS-NEXT: jr $ra
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; MIPS-NEXT: nop
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;
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; MIPSR6-LABEL: test_umin:
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; MIPSR6: # %bb.0: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: .LBB3_1: # %entry
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; MIPSR6-NEXT: # =>This Inner Loop Header: Depth=1
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; MIPSR6-NEXT: lld $2, 0($4)
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; MIPSR6-NEXT: sltu $3, $2, $5
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; MIPSR6-NEXT: selnez $1, $2, $3
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; MIPSR6-NEXT: seleqz $3, $5, $3
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; MIPSR6-NEXT: or $1, $1, $3
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; MIPSR6-NEXT: scd $1, 0($4)
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; MIPSR6-NEXT: beqzc $1, .LBB3_1
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; MIPSR6-NEXT: # %bb.2: # %entry
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; MIPSR6-NEXT: sync
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; MIPSR6-NEXT: jrc $ra
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entry:
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%0 = atomicrmw umin i64* %ptr, i64 %val seq_cst
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ret i64 %0
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}
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