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llvm-project/llvm/test/CodeGen/RISCV/sadd_sat.ll

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[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
declare i4 @llvm.sadd.sat.i4(i4, i4)
declare i8 @llvm.sadd.sat.i8(i8, i8)
declare i16 @llvm.sadd.sat.i16(i16, i16)
declare i32 @llvm.sadd.sat.i32(i32, i32)
declare i64 @llvm.sadd.sat.i64(i64, i64)
define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
; RV32I-LABEL: func:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: add a3, a0, a1
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: bgez a3, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: slt a2, a3, a2
; RV32I-NEXT: slti a1, a1, 0
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV) This pattern occurs when lowering for overflow operations introduce an xor after select_cc has already been formed. I had to rework another combine that looked for select_cc of an xor with 1. That xor will now get combined away so we just need to look for the RHS of the select_cc being 1. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D98130
2021-03-08 01:29:54 +08:00
; RV32I-NEXT: bne a1, a2, .LBB0_4
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB0_4:
; RV32I-NEXT: ret
;
; RV64I-LABEL: func:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: bge a0, a2, .LBB0_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: bge a1, a0, .LBB0_4
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_3:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: blt a1, a0, .LBB0_2
; RV64I-NEXT: .LBB0_4:
; RV64I-NEXT: lui a0, 524288
; RV64I-NEXT: ret
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
;
; RV32IZbb-LABEL: func:
; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: mv a2, a0
; RV32IZbb-NEXT: add a3, a0, a1
; RV32IZbb-NEXT: lui a0, 524288
; RV32IZbb-NEXT: bgez a3, .LBB0_2
; RV32IZbb-NEXT: # %bb.1:
; RV32IZbb-NEXT: addi a0, a0, -1
; RV32IZbb-NEXT: .LBB0_2:
; RV32IZbb-NEXT: slt a2, a3, a2
; RV32IZbb-NEXT: slti a1, a1, 0
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV) This pattern occurs when lowering for overflow operations introduce an xor after select_cc has already been formed. I had to rework another combine that looked for select_cc of an xor with 1. That xor will now get combined away so we just need to look for the RHS of the select_cc being 1. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D98130
2021-03-08 01:29:54 +08:00
; RV32IZbb-NEXT: bne a1, a2, .LBB0_4
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: mv a0, a3
; RV32IZbb-NEXT: .LBB0_4:
; RV32IZbb-NEXT: ret
;
; RV64IZbb-LABEL: func:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: lui a1, 524288
; RV64IZbb-NEXT: addiw a2, a1, -1
; RV64IZbb-NEXT: min a0, a0, a2
; RV64IZbb-NEXT: max a0, a0, a1
; RV64IZbb-NEXT: ret
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
ret i32 %tmp;
}
define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32I-LABEL: func2:
; RV32I: # %bb.0:
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: mv a4, a1
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: add a5, a4, a3
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV32I-NEXT: add a0, a0, a2
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: sltu a1, a0, a1
; RV32I-NEXT: add a2, a5, a1
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: bgez a2, .LBB1_2
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV32I-NEXT: # %bb.1:
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: addi a1, a1, -1
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV32I-NEXT: .LBB1_2:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-25 01:36:28 +08:00
; RV32I-NEXT: xor a5, a4, a2
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: xor a3, a4, a3
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-25 01:36:28 +08:00
; RV32I-NEXT: not a3, a3
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: and a3, a3, a5
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-25 01:36:28 +08:00
; RV32I-NEXT: bltz a3, .LBB1_4
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a1, a2
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV32I-NEXT: ret
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32I-NEXT: .LBB1_4:
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV32I-NEXT: srai a0, a2, 31
; RV32I-NEXT: ret
;
; RV64I-LABEL: func2:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: add a3, a0, a1
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: bgez a3, .LBB1_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: slt a2, a3, a2
; RV64I-NEXT: slti a1, a1, 0
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV) This pattern occurs when lowering for overflow operations introduce an xor after select_cc has already been formed. I had to rework another combine that looked for select_cc of an xor with 1. That xor will now get combined away so we just need to look for the RHS of the select_cc being 1. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D98130
2021-03-08 01:29:54 +08:00
; RV64I-NEXT: bne a1, a2, .LBB1_4
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB1_4:
; RV64I-NEXT: ret
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
;
; RV32IZbb-LABEL: func2:
; RV32IZbb: # %bb.0:
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32IZbb-NEXT: mv a4, a1
; RV32IZbb-NEXT: mv a1, a0
; RV32IZbb-NEXT: add a5, a4, a3
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV32IZbb-NEXT: add a0, a0, a2
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32IZbb-NEXT: sltu a1, a0, a1
; RV32IZbb-NEXT: add a2, a5, a1
; RV32IZbb-NEXT: lui a1, 524288
; RV32IZbb-NEXT: bgez a2, .LBB1_2
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV32IZbb-NEXT: # %bb.1:
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32IZbb-NEXT: addi a1, a1, -1
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV32IZbb-NEXT: .LBB1_2:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-25 01:36:28 +08:00
; RV32IZbb-NEXT: xor a5, a4, a2
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32IZbb-NEXT: xor a3, a4, a3
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-25 01:36:28 +08:00
; RV32IZbb-NEXT: andn a3, a5, a3
; RV32IZbb-NEXT: bltz a3, .LBB1_4
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32IZbb-NEXT: # %bb.3:
; RV32IZbb-NEXT: mv a1, a2
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV32IZbb-NEXT: ret
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-24 01:40:30 +08:00
; RV32IZbb-NEXT: .LBB1_4:
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV32IZbb-NEXT: srai a0, a2, 31
; RV32IZbb-NEXT: ret
;
; RV64IZbb-LABEL: func2:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: mv a2, a0
; RV64IZbb-NEXT: add a3, a0, a1
; RV64IZbb-NEXT: addi a0, zero, -1
; RV64IZbb-NEXT: slli a0, a0, 63
; RV64IZbb-NEXT: bgez a3, .LBB1_2
; RV64IZbb-NEXT: # %bb.1:
; RV64IZbb-NEXT: addi a0, a0, -1
; RV64IZbb-NEXT: .LBB1_2:
; RV64IZbb-NEXT: slt a2, a3, a2
; RV64IZbb-NEXT: slti a1, a1, 0
[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV) This pattern occurs when lowering for overflow operations introduce an xor after select_cc has already been formed. I had to rework another combine that looked for select_cc of an xor with 1. That xor will now get combined away so we just need to look for the RHS of the select_cc being 1. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D98130
2021-03-08 01:29:54 +08:00
; RV64IZbb-NEXT: bne a1, a2, .LBB1_4
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
; RV64IZbb-NEXT: # %bb.3:
; RV64IZbb-NEXT: mv a0, a3
; RV64IZbb-NEXT: .LBB1_4:
; RV64IZbb-NEXT: ret
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
ret i64 %tmp;
}
define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; RV32I-LABEL: func16:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 8
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: bge a0, a1, .LBB2_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a1, 1048568
; RV32I-NEXT: bge a1, a0, .LBB2_4
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_3:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lui a1, 1048568
; RV32I-NEXT: blt a1, a0, .LBB2_2
; RV32I-NEXT: .LBB2_4:
; RV32I-NEXT: lui a0, 1048568
; RV32I-NEXT: ret
;
; RV64I-LABEL: func16:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lui a1, 8
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: bge a0, a1, .LBB2_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a1, 1048568
; RV64I-NEXT: bge a1, a0, .LBB2_4
; RV64I-NEXT: .LBB2_2:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB2_3:
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: lui a1, 1048568
; RV64I-NEXT: blt a1, a0, .LBB2_2
; RV64I-NEXT: .LBB2_4:
; RV64I-NEXT: lui a0, 1048568
; RV64I-NEXT: ret
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
;
; RV32IZbb-LABEL: func16:
; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: add a0, a0, a1
; RV32IZbb-NEXT: lui a1, 8
; RV32IZbb-NEXT: addi a1, a1, -1
; RV32IZbb-NEXT: min a0, a0, a1
; RV32IZbb-NEXT: lui a1, 1048568
; RV32IZbb-NEXT: max a0, a0, a1
; RV32IZbb-NEXT: ret
;
; RV64IZbb-LABEL: func16:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: lui a1, 8
; RV64IZbb-NEXT: addiw a1, a1, -1
; RV64IZbb-NEXT: min a0, a0, a1
; RV64IZbb-NEXT: lui a1, 1048568
; RV64IZbb-NEXT: max a0, a0, a1
; RV64IZbb-NEXT: ret
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
ret i16 %tmp;
}
define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; RV32I-LABEL: func8:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: addi a1, zero, 127
; RV32I-NEXT: bge a0, a1, .LBB3_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, zero, -128
; RV32I-NEXT: bge a1, a0, .LBB3_4
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: addi a0, zero, 127
; RV32I-NEXT: addi a1, zero, -128
; RV32I-NEXT: blt a1, a0, .LBB3_2
; RV32I-NEXT: .LBB3_4:
; RV32I-NEXT: addi a0, zero, -128
; RV32I-NEXT: ret
;
; RV64I-LABEL: func8:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, zero, 127
; RV64I-NEXT: bge a0, a1, .LBB3_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: addi a1, zero, -128
; RV64I-NEXT: bge a1, a0, .LBB3_4
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB3_3:
; RV64I-NEXT: addi a0, zero, 127
; RV64I-NEXT: addi a1, zero, -128
; RV64I-NEXT: blt a1, a0, .LBB3_2
; RV64I-NEXT: .LBB3_4:
; RV64I-NEXT: addi a0, zero, -128
; RV64I-NEXT: ret
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
;
; RV32IZbb-LABEL: func8:
; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: add a0, a0, a1
; RV32IZbb-NEXT: addi a1, zero, 127
; RV32IZbb-NEXT: min a0, a0, a1
; RV32IZbb-NEXT: addi a1, zero, -128
; RV32IZbb-NEXT: max a0, a0, a1
; RV32IZbb-NEXT: ret
;
; RV64IZbb-LABEL: func8:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: addi a1, zero, 127
; RV64IZbb-NEXT: min a0, a0, a1
; RV64IZbb-NEXT: addi a1, zero, -128
; RV64IZbb-NEXT: max a0, a0, a1
; RV64IZbb-NEXT: ret
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
ret i8 %tmp;
}
define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; RV32I-LABEL: func3:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: addi a1, zero, 7
; RV32I-NEXT: bge a0, a1, .LBB4_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, zero, -8
; RV32I-NEXT: bge a1, a0, .LBB4_4
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_3:
; RV32I-NEXT: addi a0, zero, 7
; RV32I-NEXT: addi a1, zero, -8
; RV32I-NEXT: blt a1, a0, .LBB4_2
; RV32I-NEXT: .LBB4_4:
; RV32I-NEXT: addi a0, zero, -8
; RV32I-NEXT: ret
;
; RV64I-LABEL: func3:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, zero, 7
; RV64I-NEXT: bge a0, a1, .LBB4_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: addi a1, zero, -8
; RV64I-NEXT: bge a1, a0, .LBB4_4
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_3:
; RV64I-NEXT: addi a0, zero, 7
; RV64I-NEXT: addi a1, zero, -8
; RV64I-NEXT: blt a1, a0, .LBB4_2
; RV64I-NEXT: .LBB4_4:
; RV64I-NEXT: addi a0, zero, -8
; RV64I-NEXT: ret
[RISCV] Add Zbb command lines to uadd/usub/sadd/ssub tests. The expansions of the saturating intrinsics can make use of the min(u)/max(u) instructions in Zbb.
2021-02-19 03:24:04 +08:00
;
; RV32IZbb-LABEL: func3:
; RV32IZbb: # %bb.0:
; RV32IZbb-NEXT: add a0, a0, a1
; RV32IZbb-NEXT: addi a1, zero, 7
; RV32IZbb-NEXT: min a0, a0, a1
; RV32IZbb-NEXT: addi a1, zero, -8
; RV32IZbb-NEXT: max a0, a0, a1
; RV32IZbb-NEXT: ret
;
; RV64IZbb-LABEL: func3:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: addi a1, zero, 7
; RV64IZbb-NEXT: min a0, a0, a1
; RV64IZbb-NEXT: addi a1, zero, -8
; RV64IZbb-NEXT: max a0, a0, a1
; RV64IZbb-NEXT: ret
[RISCV] Add add/sub saturation tests that exist on ARM/AArch64/X86 There have been some recent changes to the type legalization for some of these intrinsics so I thought it would be good to have coverage.
2021-02-17 02:32:06 +08:00
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
}